Semi-Custom Design of Adiabatic Adder Circuits. - V. S. Kanchana Bhaaskaran; S. Salivahanan; D. S. Emmanuel (VLSI Design, 2006)

Differential Cascode Adiabatic Logic Structure for Low Power. - V. S. Kanchana Bhaaskaran; J. P. Raina (J. Low Power Electron., 2008)

Two-Phase sinusoidal Power-Clocked Quasi-Adiabatic Logic Circuits. - V. S. Kanchana Bhaaskaran; J. P. Raina (J. Circuits Syst. Comput., 2010)

Pre-Resolve and Sense Adiabatic Logic for 100 kHz to 500 MHz Frequency Classes. - V. S. Kanchana Bhaaskaran; J. P. Raina (J. Circuits Syst. Comput., 2012)

Design and analysis of program counter using finite state machine and incrementer based logic. - M. Divya; Ritesh Belgudri; V. S. Kanchana Bhaaskaran (ICACCI, 2014)

Low power divider using vedic mathematics. - Dalal Rutwik Kishor; V. S. Kanchana Bhaaskaran (ICACCI, 2014)

Low power vedic multiplier using energy recovery logic. - Hardik Sangani; Tanay M. Modi; V. S. Kanchana Bhaaskaran (ICACCI, 2014)

Two phase sinusoidal power clocked quasi-static adiabatic logic families. - P. Sasipriya; V. S. Kanchana Bhaaskaran (IC3, 2015)

Gating techniques for 6T SRAM cell using different modes of FinFET. - Deeksha Anandani; Anurag Kumar; V. S. Kanchana Bhaaskaran (ICACCI, 2015)

Self-gated resonant-clocked flip-flop optimised for power efficiency and signal integrity. - Jennifer Judy Dominic Jawahar; Supreeth Mysore Shivananda Murthy; Kanchana Bhaaskaran Vettuvanam Somasundaram (IET Circuits Devices Syst., 2016)

Low Power, High Speed and Area Efficient Binary Count Multiplier. - Kore Sagar Dattatraya; Ritesh Belgudri; Ramdas Bhanudas Khaladkar; V. S. Kanchana Bhaaskaran (J. Circuits Syst. Comput., 2016)

Low-Power High-Accuracy Fixed-Width Radix-8 Booth Multiplier Using Probabilistic Estimation Technique. - Saroja S. Bhusare; V. S. Kanchana Bhaaskaran (J. Circuits Syst. Comput., 2017)

Design and Implementation of 32-Bit High Valency Jackson Adders. - N. Poornima; V. S. Kanchana Bhaaskaran (J. Circuits Syst. Comput., 2017)

Energy Recovery Circuit Design for Low Power VLSI. - V. S. Kanchana Bhaaskaran (iSES, 2018)

Positive Feedback Symmetric Adiabatic Logic Against Differential Power Attack. - Bhuvana B. P.; V. S. Kanchana Bhaaskaran (VLSID, 2018)

Lightweight S-Box Architecture for Secure Internet of Things. - Prathiba Ashok; Kanchana Bhaaskaran Vettuvanam Somasundaram (Inf., 2018)

Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL). - P. Sasipriya; V. S. Kanchana Bhaaskaran (J. Circuits Syst. Comput., 2018)

Design and Analysis of Clocked CMOS Differential Adiabatic Logic (CCDAL) for Low Power. - P. Sasipriya; Kanchana Bhaaskaran Vettuvanam Somasundaram (J. Low Power Electron., 2018)

Design and Analysis of FinFET Based CSCPAL Low Power Adder. - Jayashree K. G; Lois Priscilla S; Bhuvana B. P.; V. S. Kanchana Bhaaskaran (iSES, 2019)

Design impacts of delay invariant high-speed clock delayed dual keeper domino circuit. - A. Anita Angeline; V. S. Kanchana Bhaaskaran (IET Circuits Devices Syst., 2019)

Charge balancing symmetric pre-resolve adiabatic logic against power analysis attacks. - Prathiba Ashok; Kanchana Bhaaskaran Vettuvanam Somasundaram (IET Inf. Secur., 2019)

Hardware footprints of S-box in lightweight symmetric block ciphers for IoT and CPS information security systems. - Prathiba Ashok; Kanchana Bhaaskaran Vettuvanam Somasundaram (Integr., 2019)

Design of FinFET-based Energy Efficient Pass-Transistor Adiabatic Logic for ultra-low power applications. - Bhuvana B. P.; V. S. Kanchana Bhaaskaran (Microelectron. J., 2019)

Design and Analysis of Low Power and High Speed FinFET based Hybrid Full Adder/Subtractor Circuit (FHAS). - E. Ramkumar; D. Gracin; P. Rajkamal; Bhuvana B. P.; V. S. Kanchana Bhaaskaran (iSES, 2020)

Borrow Select Subtractor for Low Power and Area Efficiency. - Keshav Govindarajan; V. S. Kanchana Bhaaskaran (ISVLSI, 2020)

Analysis of FinFET-Based Adiabatic Circuits for the Design of Arithmetic Structures. - Bhuvana B. P.; V. S. Kanchana Bhaaskaran (J. Circuits Syst. Comput., 2020)

Double Edge-Triggered Tristate Flip-Flop Physical Unclonable Function for Secure IoT Ecosystem. - Hemavathy Sriramulu; V. S. Kanchana Bhaaskaran (iSES, 2021)

Design and Analysis of Secure Quasi-Adiabatic Tristate Physical Unclonable Function. - Hemavathy Sriramulu; Kanchana Bhaaskaran Vettuvanam Somasundaram (IEEE Consumer Electron. Mag., 2022)

Lightweight VLSI Architectures for Image Encryption Applications. - Prathiba Ashok; Suyash Vardhan Srivathshav; E. Ramkumar; P. Rajkamal; V. S. Kanchana Bhaaskaran (Int. J. Inf. Secur. Priv., 2022)

Arbiter PUF - A Review of Design, Composition, and Security Aspects. - Hemavathy Sriramulu; V. S. Kanchana Bhaaskaran (IEEE Access, 2023)

Adaptive PUF design to authenticate and evaluate heterogeneous IPs in edge computing. - Hemavathy Sriramulu; J. Kokila; V. S. Kanchana Bhaaskaran (J. Supercomput., 2024)

Unified Security Framework Using Device-Specific Fingerprint: Mitigating Hardware Trojans and Authenticating Firmware Updates. - Hemavathy Sriramulu; Kokila Jagadeesh; V. S. Kanchana Bhaaskaran (IEEE Access, 2025)