Low Power Design Analysis of PLL Components in Submicron Technology. - Kanika Garg; V. Sulochana Verma (ACITY (3), 2012)

Reduction of Crosstalk Noise and Delay in VLSI Interconnects Using Schmitt Trigger as a Buffer and Wire Sizing. - Shikha Singh 004; V. Sulochana Verma (ACITY (3), 2012)