A parallel elliptic curve crypto-processor architecture with reduced clock cycle for FPGA platforms. - Murugesan Kalaiarasi; Vepadappu Raman Venkatasubramani; V. Vinoth Thyagarajan; S. Rajaram 001 (J. Supercomput., 2022)

Low Latency Binary Edward Curve Crypto Processor for FPGA Platforms. - J. Adline Vidhya; V. R. Venkatasubramani; S. Rajaram 001; V. Vinoth Thyagarajan; M. S. K. Manikandan (ATIS, 2024)