Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes. - V. Bharath Sreenivasulu; Vadthiya Narendar (Microelectron. J., 2021)

On the design of p-channel step-FinFET at sub-10nm node: A parametric analysis. - Santosh Kumar Padhi; Vadthiya Narendar; Atul Kumar Nishad (Microelectron. J., 2022)

NDR free negative capacitance CGAAFET at 2nm technology node for low power and high-speed applications. - Ravi Kothapally; Vadthiya Narendar; Satish Maheshwaram (Microelectron. J., 2023)

Performance analysis of geometric variations in circular double gate MOSFETs at sub-7nm technology nodes. - Kallepelli Sagar; Satish Maheshwaram; Vadthiya Narendar (Microelectron. J., 2023)

Study of HeavyIon Irradiation Effects in FinFETs at Sub-5 nm Technology Node: Reliability Perspective. - Sresta Valasa; Venkata Ramakrishna Kotha; Sunitha Bhukya; Vadthya Bheemudu; Shubham Tayal; Vadthiya Narendar (VDAT, 2024)

A novel step architecture based negative capacitance (SNC) FET: Design and circuit level analysis. - Santosh Kumar Padhi; Vadthiya Narendar; Atul Kumar Nishad (Microelectron. J., 2024)