A 500 mV to 1.0 V 128 Kb SRAM in Sub 20 nm Bulk-FinFET Using Auto-adjustable Write Assist. - Prashant Dubey; Gaurav Ahuja; Vaibhav Verma; Sanjay Kumar Yadav; Amit Khanuja (VLSID, 2014)

A 128-kb 10% power reduced 1T high density ROM with 0.56 ns access time using bitline edge sensing in sub 16nm bulk FinFET technology. - Vaibhav Verma; Sachin Taneja; Pritender Singh; Sanjeev Kumar Jain (SoCC, 2015)

Back to the Future: Digital Circuit Design in the FinFET Era. - Xinfei Guo; Vaibhav Verma; Patricia Gonzalez-Guerrero; Sergiu Mosanu; Mircea R. Stan (J. Low Power Electron., 2017)

SRAM based opportunistic energy efficiency improvement in dual-supply near-threshold processors. - Yunfei Gu; Dengxue Yan; Vaibhav Verma; Mircea R. Stan; Xuan Zhang 001 (DAC, 2018)

When "things" get older: Exploring circuit aging in IoT applications. - Xinfei Guo; Vaibhav Verma; Patricia Gonzalez-Guerrero; Mircea R. Stan (ISQED, 2018)

eAP: A Scalable and Efficient In-Memory Accelerator for Automata Processing. - Elaheh Sadredini; Reza Rahimi; Vaibhav Verma; Mircea Stan; Kevin Skadron (MICRO, 2019)

A Scalable and Efficient In-Memory Interconnect Architecture for Automata Processing. - Elaheh Sadredini; Reza Rahimi; Vaibhav Verma; Mircea Stan; Kevin Skadron (IEEE Comput. Archit. Lett., 2019)

Comparative Analysis and Implementation of Single-ended Sense Amplifier Schemes using 65nm LSTP CMOS Technology. - Vaibhav Verma; Fiza Akhtar; Anuj Grover (VDAT, 2020)

ATCPiM: Analog to Time Coded Processing in Memory for IoT at the Edge. - Mohammad Nazmus Sakib; Rahul Sreekumar; Vaibhav Verma; Tommy Tracy II; Mircea R. Stan (WF-IoT, 2021)

EXTREM-EDGE - EXtensions To RISC-V for Energy-efficient ML inference at the EDGE of IoT. - Vaibhav Verma; Tommy Tracy II; Mircea R. Stan (Sustain. Comput. Informatics Syst., 2022)

Design Space Exploration of Layer-Wise Mixed-Precision Quantization with Tightly Integrated Edge Inference Units. - Xiaotian Zhao; Yimin Gao; Vaibhav Verma; Ruge Xu; Mircea Stan; Xinfei Guo (ACM Great Lakes Symposium on VLSI, 2023)

LiteAIR5: A System-Level Framework for the Design and Modeling of AI-extended RISC-V Cores. - Yimin Gao; Sergiu Mosanu; Mohammad Nazmus Sakib; Vaibhav Verma; Xinfei Guo; Mircea Stan (SOCC, 2023)