Area and power efficient DCT architecture for image compression. - Vaithiyanathan Dhandapani; Seshasayanan Ramachandran (EURASIP J. Adv. Signal Process., 2014)

Power-optimized log-based image processing system. - Vaithiyanathan Dhandapani; Seshasayanan Ramachandran (EURASIP J. Image Video Process., 2014)

Fuzzy decision support system for improving the crop productivity and efficient use of fertilizers. - G. Prabakaran; D. Vaithiyanathan 001; Madhavi Ganesan (Comput. Electron. Agric., 2018)

Performance Analysis of 8-Point Approximate DCT Architecture Using Conventional and Hybrid Adders. - D. Vaithiyanathan 001; Rajhans Kolhe; Alok Kumar Mishra 001; Britto Pari James; K. Kunaraj (iSES, 2020)

Performance analysis of dynamic CMOS circuit based on node-discharger and twist-connected transistors. - Vaithiyanathan Dhandapani; Ravindra Kumar; Ashima Rai; Khushboo Sharma (IET Comput. Digit. Tech., 2020)

Synchrosqueezing Transform Based Powerline Interference Reduction in ECG Recording. - M. Suresh Kumar; G. Krishnamoorthy; D. Vaithiyanathan 001 (J. Medical Imaging Health Informatics, 2020)

Internet of Things Integrated with Multi-level Authentication for Secured IoT Data Stream Through TLS/SSL Layer. - Yuvaraj S.; Manigandan Muniraj; Vaithiyanathan Dhandapani; R. Saajid; S. Nikhilesh (BDA (Astronomy, Science, and Engineering), 2021)

Design and analysis of ultra-low power 18T adaptive data track flip-flop for high-speed application. - Alok Kumar Mishra 001; Vaithiyanathan Dhandapani; Urvashi Chopra (Int. J. Circuit Theory Appl., 2021)

Underwater image enhancement by combining color constancy and dehazing based on depth estimation. - Manigandan Muniraj; Vaithiyanathan Dhandapani (Neurocomputing, 2021)

Signal Processing and Classification for Electroencephalography Based Motor Imagery Brain Computer Interface. - A. Shankar; S. Muttan; D. Vaithiyanathan 001 (J. Medical Imaging Health Informatics, 2021)

FPGA based effective agriculture productivity prediction system using fuzzy support vector machine. - G. Prabakaran; D. Vaithiyanathan 001; Madhavi Ganesan (Math. Comput. Simul., 2021)

Underwater image enhancement by color correction and color constancy via Retinex for detail preserving. - Manigandan Muniraj; Vaithiyanathan Dhandapani (Comput. Electr. Eng., 2022)

Design and Analysis of Soft Error Rate in FET/CNTFET Based Radiation Hardened SRAM Cell. - Bharathi Raj Muthu; Ewins Pon Pushpa; Vaithiyanathan Dhandapani; Kamala Jayaraman; Hemalatha Vasanthakumar; Won-Chun Oh; Suresh Sagadevan (Sensors, 2022)

FPGA based intelligent embedded system for predicting the productivity using fuzzy logic. - G. Prabakaran; D. Vaithiyanathan 001; Madhavi Ganesan (Sustain. Comput. Informatics Syst., 2022)

A Partially Static High Frequency 18T Hybrid Topological Flip-Flop Design for Low Power Application. - Alok Kumar Mishra 001; Urvashi Chopra; D. Vaithiyanathan 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A1RL: Approximate 1-Row-LUT-Based Low-Power Signed Multipliers for DSP and Machine Learning Applications on FPGAs. - Zainab Aizaz; Kavita Khare; Mohd Anas Khan; Mahesh Kumar Singh; Vaithiyanathan Dhandapani (APCCAS, 2023)

VLSI Implementation of Reconfigurable Canny Edge Detection Algorithm. - K. K. Senthilkumar; E. Avantika; B. Gayathri; Vaithiyanathan Dhandapani (BDA (Astronomy, Science, and Engineering), 2023)

Underwater image enhancement by modified color correction and adaptive Look-Up-Table with edge-preserving filter. - Manigandan Muniraj; Vaithiyanathan Dhandapani (Signal Process. Image Commun., 2023)

Architectural analysis of 1-D to 2-D array conversion of priority encoder. - Alok Kumar Mishra 001; Shail Anand; Nishant Singh; Vaithiyanathan Dhandapani; Baljit Kaur (Int. J. Syst. Assur. Eng. Manag., 2023)

Comparative Study Of GAA-JL Transistor With And Without FE Material For Hydrogen Gas Sensing. - Ashish Verma; Preeti Verma; Vaithiyanathan Dhandapani (VDAT, 2024)

Design insights into a junctionless nanosheet FET (JL-NSFET) for switching and Analog/RF applications: Device to circuit level assessment. - Vadthya Bheemudu; Vaithiyanathan Dhandapani; Baljit Kaur (Microelectron. J., 2024)

High speed and area efficient coded input BCSM shared LUT-based FIR filter architecture. - S. C. Prasanna; Britto Pari James; Vaithiyanathan Dhandapani (Int. J. Syst. Assur. Eng. Manag., 2024)