FPGA technology mapping with encoded libraries andstaged priority cuts. - Andrew A. Kennings; Kristofer Vorwerk; Arun Kundu; Val Pevzner; Andy Fox (FPGA, 2009)

Physical optimization for FPGAs using post-placement topology rewriting. - Val Pevzner; Andrew A. Kennings; Andy Fox (ISPD, 2009)

Efficient FPGA Resynthesis Using Precomputed LUT Structures. - Andrew A. Kennings; Alan Mishchenko; Kristofer Vorwerk; Val Pevzner; Arun Kundu (FPL, 2010)

Power minimisation during field programmable gate array placement. - Kristofer Vorwerk; Andrew A. Kennings; Val Pevzner; Arun Kundu; Madhu Raman; Julien Dunoyer; Yaun-shung Hsu (IET Comput. Digit. Tech., 2010)

A 65nm flash-based FPGA fabric optimized for low cost and power. - Jonathan W. Greene; Sinan Kaptanoglu; Wenyi Feng; Volker Hecht; Joel Landry; Fei Li 003; Anton Krouglyanskiy; Mihai Morosan; Val Pevzner (FPGA, 2011)

FPGA technology mapping with encoded libraries and staged priority cuts. - Andrew A. Kennings; Kristofer Vorwerk; Arun Kundu; Val Pevzner; Andy Fox (ACM Trans. Reconfigurable Technol. Syst., 2011)

Rent's rule based FPGA packing for routability optimization. - Wenyi Feng; Jonathan W. Greene; Kristofer Vorwerk; Val Pevzner; Arun Kundu (FPGA, 2014)