Rajah: The Design of a Chess Program. - Valavan Manohararajah (J. Int. Comput. Games Assoc., 1997)

Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices. - Valavan Manohararajah; Terry P. Borer; Stephen Dean Brown; Zvonko G. Vranesic (FPL, 2002)

Two-stage physical synthesis for FPGAs. - Deshanand P. Singh; Valavan Manohararajah; Stephen Dean Brown (CICC, 2005)

Incremental retiming for FPGA physical synthesis. - Deshanand P. Singh; Valavan Manohararajah; Stephen Dean Brown (DAC, 2005)

Post-Placement BDD-Based Decomposition for FPGAs. - Valavan Manohararajah; Deshanand P. Singh; Stephen Dean Brown (FPL, 2005)

Adaptive FPGAs: High-Level Architecture and a Synthesis Method. - Valavan Manohararajah; Stephen Dean Brown; Zvonko G. Vranesic (FPL, 2006)

Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. - Gordon R. Chiu; Deshanand P. Singh; Valavan Manohararajah; Stephen Dean Brown (ICCAD, 2006)

Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. - Valavan Manohararajah; Gordon R. Chiu; Deshanand P. Singh; Stephen Dean Brown (SLIP, 2006)

Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping. - Valavan Manohararajah; Stephen Dean Brown; Zvonko G. Vranesic (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. - Valavan Manohararajah; Gordon R. Chiu; Deshanand P. Singh; Stephen Dean Brown (IEEE Trans. Very Large Scale Integr. Syst., 2007)

The Stratix™ 10 Highly Pipelined FPGA Architecture. - David M. Lewis; Gordon R. Chiu; Jeffrey Chromczak; David R. Galloway; Ben Gamsa; Valavan Manohararajah; Ian Milton; Tim Vanderhoek; John Van Dyken (FPGA, 2016)

SD2: Self-Distilled Sparse Drafters. - Mike Lasby; Nish Sinnadurai; Valavan Manohararajah; Sean Lie; Vithursan Thangarasa (CoRR, 2025)