A floating-point systolic array processing element with serial communication and built-in self-test. - T. C. Davies; Dhamin Al-Khalili; Valek Szwarc (J. VLSI Signal Process., 1994)

A chip set for pipeline and parallel pipeline FFT architectures. - Valek Szwarc; Luc Desormeaux; Wilson Wong; Clifford P. S. Yeung; Chong H. Chan; Tad A. Kwasniewski (J. VLSI Signal Process., 1994)

A High-Speed, Real-to-Quadrature Converter with Filtering and Decimation. - Luc Desormeaux; Valek Szwarc; John H. Lodge (Great Lakes Symposium on VLSI, 1996)

A High Performance Soft Decision Viterbi Decoder for Wlan and Broadband Applications. - Abdul-Rafeeq Abdul-Shakoor; Valek Szwarc (CCECE, 2006)

A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications. - Huong Ho; Valek Szwarc; Tad A. Kwasniewski (Int. J. Reconfigurable Comput., 2009)

Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination. - Huong Ho; Valek Szwarc; Tad A. Kwasniewski (J. Signal Process. Syst., 2010)