A 14b 2.5GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction. - Brian Setterberg; Ken Poulton; Sourja Ray; Dan J. Huber; Valentin Abramzon; Guenter Steinbach; John P. Keane; Bernd Wuppermann; Mathew Clayson; Matthew Martin; Rizwan Pasha; Edda Peeters; et al. (ISSCC, 2013)

A CMOS-compatible boosted transistor having >2× drive current and low leakage current. - Jin-Woo Han; Victor Moroz; Andrey Kucherov; Dinesh Maheshwari; Valentin Abramzon; Zvi Or-Bach; Yoshio Nishi; Yuniarto Widjaja (ESSDERC, 2016)

A 1.5pJ/bit, 5-to-10Gbps Forwarded-Clock I/O with Per-Lane Clock De-Skew in a Low Power 28nm CMOS Process. - Anup P. Jose; Valentin Abramzon; Mohamed Elzeftawi; Michael Wang; Kyunglok Kim; Younghoon Song; Shiva Moballegh; Jalil Kamali; Amir Amirkhany (CICC, 2019)