Recovering Information on the CVA6 RISC-V CPU with a Baremetal Micro-Architectural Covert Channel. - Valentin Martinoli; Yannick Teglia; Abdellah Bouagoun; Régis Leveugle (IOLTS, 2022)

CVA6's Data cache: Structure and Behavior. - Valentin Martinoli; Yannick Teglia; Abdellah Bouagoun; Régis Leveugle (CoRR, 2022)

Secured Bus as a Countermeasure against Covert Channels: NEORV32 Case Study. - Régis Leveugle; Nathan Hocquette; Charles Labarre; Romain Plumaugat; Loic Tcharoukian; Valentin Martinoli; Yannick Teglia (LATS, 2024)