Distribution-graph based approach and extended tree growing technique in power-constrained block-test scheduling. - Valentin Muresan; Xiaojun Wang 001; Valentina Muresan; Mircea Vladutiu (Asian Test Symposium, 2000)

The left edge algorithm in block test scheduling under power constraints. - Valentin Muresan; Xiaojun Wang 001; Mircea Vladutiu (ISCAS, 2000)

A comparison of classical scheduling approaches in power-constrained block-test scheduling. - Valentin Muresan; Xiaojun Wang 001; Valentina Muresan; Mircea Vladutiu (ITC, 2000)

Power-Constrained Block-Test List Scheduling. - Valentin Muresan; Xiaojun Wang 001; Valentina Muresan; Mircea Vladutiu (IEEE International Workshop on Rapid System Prototyping, 2000)

The Left Edge Algorithm and the Tree Growing Technique in Block-Test Scheduling under Power Constraints. - Valentin Muresan; Xiaojun Wang 001; Valentina Muresan; Mircea Vladutiu (VTS, 2000)

Mixed Classical Scheduling Algorithms and Tree Growing Technique in Block-Test Scheduling under Power Constraints. - Valentin Muresan; Xiaojun Wang 001; Valentina Muresan; Mircea Vladutiu (IEEE International Workshop on Rapid System Prototyping, 2001)

Energy-Efficient Hardware Architecture for Variable N-point 1D DCT. - Andrew Kinane; Valentin Muresan; Noel E. O'Connor; Noel Murphy; Seán Marlow (PATMOS, 2004)

Greedy Tree Growing Heuristics on Block-Test Scheduling Under Power Constraints. - Valentin Muresan; Xiaojun Wang 001; Valentina Muresan; Mircea Vladutiu (J. Electron. Test., 2004)

FPGA-Based Conformance Testing and System Prototyping of an MPEG-4 SA-DCT Hardware Accelerator. - Andrew Kinane; Alan Casey; Valentin Muresan; Noel E. O'Connor (FPT, 2005)

Optimisation of Constant Matrix Multiplication Operation Hardware Using a Genetic Algorithm. - Andrew Kinane; Valentin Muresan; Noel E. O'Connor (EvoWorkshops, 2006)

Towards an optimised VLSI design algorithm for the constant matrix multiplication problem. - Andrew Kinane; Valentin Muresan; Noel E. O'Connor (ISCAS, 2006)

A low complexity hardware architecture for motion estimation. - Daniel Larkin; Valentin Muresan; Noel E. O'Connor (ISCAS, 2006)

An Efficient Hardware Architecture for a Neural Network Activation Function Generator. - Daniel Larkin; Andrew Kinane; Valentin Muresan; Noel E. O'Connor (ISNN (2), 2006)

Requirements of a real-time multiprocessor operating system for multimedia applications. - Valentin Stangaciu; Georgiana Macariu; Mihai V. Micea; Valentin Muresan; Brendan Barry (SACI, 2011)

Superior vision: Always on human-like vision for intelligent devices. - Valentin Muresan (SACI, 2016)