Survivable Discrete Circuits Design. - Anzhela Yu. Matrosova; Valentina Andreeva; Yu. Sedov (IOLTW, 2002)

Test minimization technique for multiple stuck-at faults of combinational circuit. - Valentina Andreeva (EWDTS, 2010)

Test set compaction procedure for combinational circuits based on decomposition tree. - Valentina Andreeva (EWDTS, 2011)

A research of heuristic optimization approaches to the test set compaction procedure based on a decomposition tree for combinational circuits. - Valentina Andreeva; Kirill A. Sorudeykin (EWDTS, 2013)

Decomposition tree - based compaction procedure with iteration steps for interconversional layouts of tasks. - Valentina Andreeva; Kirill A. Sorudeykin (EWDTS, 2014)

Fully delay and multiple stuck-at faults testable FSM design. - Anzhela Yu. Matrosova; Valentina Andreeva; V. Tomkov (EWDTS, 2015)

Patching circuit design based on reserved CLBs. - Anjela Yu. Matrosova; Sergey Ostanin; Valentina Andreeva (AQTR, 2016)

ROBDDs application for finding the shortest transfer sequence of sequential circuit or only revealing existence of this sequence without deriving the sequence itself. - Anzhela Yu. Matrosova; Valentina Andreeva; Alexey Melnikov 002 (EWDTS, 2016)

Finding the shortest transfer sequence of sequential circuit based on simplified ROBDDs. - Valentina Andreeva; Semyon Chernyshov (EWDTS, 2017)

Fault-Tolerant Synchronous FSM Network Design for Path Delay Faults. - Sergey Ostanin; Valentina Andreeva; Natalia Butorina; D. Tretyakov (EWDTS, 2018)

Deriving Low Power Test Sequences Detecting Robust Testable PDFs. - Anjela Yu. Matrosova; Valentina Andreeva; V. Tychinskiy (EWDTS, 2019)

SAT Solvers Application of Deriving All Test Pairs Detecting Robust Testable PDFs. - Anjela Yu. Matrosova; Valentina Andreeva; V. Tychinskiy (EWDTS, 2021)

Deriving FSM-based tests using $a, b- text{faults}$ for Logic Circuits. - Andrey Laputenko; Nina Yevtushenko 001; Valentina Andreeva; Anzhela Yu. Matrosova (ISVLSI, 2022)