Logic Circuit Speeding up through Multiplexing. - Valeri F. Tomashau (FPL, 1999)

Efficient 4-input LUTs FPGA implementation of combinatorial multiplier over canonical base GF(16). - Valeri F. Tomashau (FPT, 2002)

Validation of an Advanced Encryption Standard (AES) IP Core. - Valeri F. Tomashau; Tom Kean (FCCM, 2004)