High-speed, high-reliability circuit design for megabit DRAM. - Peter Gillingham; Richard C. Foss; Valerie Lines; Gregg Shimokura; Tomasz Wojcicki (IEEE J. Solid State Circuits, 1991)

66MHz 2.3M Ternary Dynamic Content Addressable Memory. - Valerie Lines; Abdullah Ahmed; Peter Ma; Stanley Ma; Robert McKenzie; Hong-Seok Kim; Cynthia Mar (MTDT, 2000)

A 1GHz embedded DRAM macro and fully programmable BIST with at-speed bitmap capability. - Valerie Lines; Robert McKenzie; Hakjune Oh; Hong-Beom Pyeon; Matthew Dunn; Susan Palapar; Susan Coleman; Peter Nyasulu; Tony Mai; Seanna Pike; John McCready; Jody Defazio; et al. (MTDT, 2005)