A novel test and analysis scheme to elucidate tail bit characteristics in STT-MRAM arrays. - W. Kim; Valerio Pica; N. Jossart; Farrukh Yasin; Kurt Wostyn; S. Couet; Sidharth Rao (IMW, 2024)

Extremely Scaled Perpendicular SOT-MRAM Array Integration on 300mm Wafer. - Farrukh Yasin; A. Palomino; A. Kumar; Valerio Pica; Simon Van Beek; Giacomo Talmelli; Van D. Nguyen; Stefan Cosemans; D. Crotti; Kurt Wostyn; Gouri Sankar Kar; Sebastien Couet (VLSI Technology and Circuits, 2024)

Soft and Hard Error-Correction Techniques in STT-MRAM. - Surendra Hemaram; Mehdi B. Tahoori; Francky Catthoor; Siddharth Rao; Sebastien Couet; Valerio Pica; Gouri Sankar Kar (IEEE Des. Test, 2024)