NBTI effects on tree-like clock distribution networks. - Wei Liu 016; Sandeep Miryala; Valerio Tenace; Andrea Calimera; Enrico Macii; Massimo Poncino (ACM Great Lakes Symposium on VLSI, 2012)

Pass-XNOR logic: A new logic style for P-N junction based graphene circuits. - Valerio Tenace; Andrea Calimera; Enrico Macii; Massimo Poncino (DATE, 2014)

Row-based body-bias assignment for dynamic thermal clock-skew compensation. - Valerio Tenace; Sandeep Miryala; Andrea Calimera; Alberto Macii; Enrico Macii; Massimo Poncino (Microelectron. J., 2014)

One-pass logic synthesis for graphene-based Pass-XNOR logic circuits. - Valerio Tenace; Andrea Calimera; Enrico Macii; Massimo Poncino (DAC, 2015)

Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization. - Sandeep Miryala; Valerio Tenace; Andrea Calimera; Enrico Macii; Massimo Poncino; Luca Gaetano Amarù; Giovanni De Micheli; Pierre-Emmanuel Gaillardon (ACM Great Lakes Symposium on VLSI, 2015)

Ultra-low power circuits using graphene p-n junctions and adiabatic computing. - Sandeep Miryala; Valerio Tenace; Andrea Calimera; Enrico Macii; Massimo Poncino (Microprocess. Microsystems, 2015)

Graphene-PLA (GPLA): a Compact and Ultra-Low Power Logic Array Architecture. - Valerio Tenace; Andrea Calimera; Enrico Macii; Massimo Poncino (ACM Great Lakes Symposium on VLSI, 2016)

Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies. - Valerio Tenace; Andrea Calimera; Enrico Macii; Massimo Poncino (ISCAS, 2016)

Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits. - Valerio Tenace; Andrea Calimera; Enrico Macii; Massimo Poncino (VLSI-SoC, 2016)

Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits. - Valerio Tenace; Andrea Calimera; Enrico Macii; Massimo Poncino (VLSI-SoC (Selected Papers), 2016)

Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs. - Valerio Tenace; Andrea Calimera; Enrico Macii; Massimo Poncino (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

CAD Tools for Graphene-Based Electronic Circuits. - Valerio Tenace (2016)

Activation-Kernel Extraction through Machine Learning. - Valerio Tenace; Andrea Calimera (NGCAS, 2017)

A compression-driven training framework for embedded deep neural networks. - Matteo Grimaldi; Federico Pugliese; Valerio Tenace; Andrea Calimera (INTESA@ESWEEK, 2018)

Multiplication by Inference using Classification Trees: A Case-Study Analysis. - Roberto Giorgio Rizzo; Valerio Tenace; Andrea Calimera (ISCAS, 2018)

Inferential Logic: a Machine Learning Inspired Paradigm for Combinational Circuits. - Valerio Tenace; Andrea Calimera (VLSI-SoC, 2018)

Quasi-exact logic functions through classification trees. - Valerio Tenace; Andrea Calimera (Integr., 2018)

Energy-Efficient Convolutional Neural Networks via Recurrent Data Reuse. - Luca Mocerino; Valerio Tenace; Andrea Calimera (DATE, 2019)

SAID: A Supergate-Aided Logic Synthesis Flow for Memristive Crossbars. - Valerio Tenace; Roberto Giorgio Rizzo; Debjyoti Bhattacharjee; Anupam Chattopadhyay; Andrea Calimera (DATE, 2019)

Layer-Wise Compressive Training for Convolutional Neural Networks. - Matteo Grimaldi; Valerio Tenace; Andrea Calimera (Future Internet, 2019)

Logic Synthesis of Pass-Gate Logic Circuits With Emerging Ambipolar Technologies. - Valerio Tenace; Andrea Calimera; Enrico Macii; Massimo Poncino (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

NEMO-CNN: An Efficient Near-Memory Accelerator for Convolutional Neural Networks. - Grant Brown; Valerio Tenace; Pierre-Emmanuel Gaillardon (ASAP, 2021)

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. - Shubham Rai; Walter Lau Neto; Yukio Miyasaka; Xinpei Zhang; Mingfei Yu; Qingyang Yi; Masahiro Fujita; Guilherme B. Manske; Matheus F. Pontes; Leomar S. da Rosa; Marilton S. de Aguiar; Paulo F. Butzen; et al. (DATE, 2021)

AIvril: AI-Driven RTL Generation With Verification In-The-Loop. - Mubashir ul Islam; Humza Sami; Pierre-Emmanuel Gaillardon; Valerio Tenace (CoRR, 2024)

EDA-Aware RTL Generation with Large Language Models. - Mubashir ul Islam; Humza Sami; Pierre-Emmanuel Gaillardon; Valerio Tenace (DATE, 2025)

Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation. - Humza Sami; Mubashir ul Islam; Samy Charas; Asav Gandhi; Pierre-Emmanuel Gaillardon; Valerio Tenace (CoRR, 2025)

Adaptive Multi-Agent Reasoning via Automated Workflow Generation. - Humza Sami; Mubashir ul Islam; Pierre-Emmanuel Gaillardon; Valerio Tenace (CoRR, 2025)