FSM State Assignment Methods for Low-Power Design. - Valery Salauyou; Tomasz Grzes (CISIM, 2007)

The Synthesis of Combined Mealy and Moore Machines Structural Model Using Values of Output Variables as Codes of States. - Adam Klimowicz; Valery Salauyou (DSD, 2012)

Designing of Hierarchical Structures for Binary Comparators on FPGA/SoC. - Valery Salauyou; Marek Gruszewski (CISIM, 2015)

Synthesis of High-Speed Finite State Machines in FPGAs by State Splitting. - Valery Salauyou (CISIM, 2016)

State Assignment of Finite-State Machines by Using the Values of Input Variables. - Valery Salauyou; Michal Ostapczuk (CISIM, 2017)

Synthesis of High-Speed ASM Controllers with Moore Outputs by Introducing Additional States. - Valery Salauyou; Irena Bulatowa (CISIM, 2018)

High-Speed Finite State Machine Design by State Splitting. - Damian Borecki; Valery Salauyou; Tomasz Grzes (DepCoS-RELCOMEX, 2018)

Coding Techniques in Verilog for Finite State Machine Designs in FPGA. - Valery Salauyou; Lukasz Zabrocki (CISIM, 2019)

The Synthesis Method of High-Speed Finite State Machines in FPGA. - Valery Salauyou; Damian Borecki; Tomasz Grzes (CISIM, 2020)

Digital Device Design by ASMD-FSMD Technique. - Valery Salauyou; Adam Klimowicz (CISIM, 2021)

Embedded Processor Design in FPGA by ASMD-FSMD and FSM-Single Techniques. - Valery Salauyou (CISIM, 2022)

Fault Detection of Moore Finite State Machines by Structural Models. - Valery Salauyou (CISIM, 2023)

Complexity of Area and Performance Estimates of Finite State Machines. - Valery Salauyou (CISIM, 2025)