Novel All-Pass Section for High-Performance Signal Processing Using CMOS DCCII. - Taaha Nizam; Vallabhuni Vijay; Avireni Srinivasulu; Dipankar Pal (TENCON, 2021)

ECG performance validation using operational transconductance amplifier with bias current. - Vallabhuni Vijay; C. V. Sai Kumar Reddy; Chandra Shaker Pittala; Rajeev Ratna Vallabhuni; M. Saritha; M. Lavanya; S. China Venkateswarlu; Menda Sreevani (Int. J. Syst. Assur. Eng. Manag., 2021)

Road Identification Through Efficient Edge Segmentation Based on Morphological Operations. - Bandi Mary Sowbhagya Rani; Vasumathi Devi Majety; Chandra Shaker Pittala; Vallabhuni Vijay; Kanumalli Satya Sandeep; Siripuri Kiran (Traitement du Signal, 2021)

Double-threshold energy detection: noisy environment applied cognitive radio. - Kancharapu Chaitanya; Mohammad Khadir; S. Sushma; Lavanya Nalla; G. Naveen; Nandi Manjula; M. Saritha; M. Lavanya; Mulinti Narendra Reddy; Vallabhuni Vijay (Int. J. Syst. Assur. Eng. Manag., 2022)

Numerical analysis of various plasmonic MIM/MDM slot waveguide structures. - Chandra Shaker Pittala; Rajeev Ratna Vallabhuni; Vallabhuni Vijay; Usha Rani Anam; Kancharapu Chaitanya (Int. J. Syst. Assur. Eng. Manag., 2022)

A VLSI design of clock gated technique based ADC lock-in amplifier. - M. Saritha; M. Lavanya; G. Ajitha; Mulinti Narendra Reddy; P. Annapurna; Menda Sreevani; S. Swathi; S. Sushma; Vallabhuni Vijay (Int. J. Syst. Assur. Eng. Manag., 2022)

A hierarchical image matting model for blood vessel segmentation in retinal images. - S. Swathi; S. Sushma; C. Devi Supraja; V. Bindusree; L. Babitha; Vallabhuni Vijay (Int. J. Syst. Assur. Eng. Manag., 2022)

Design and performance analysis of low power and energy-efficient vedic multipliers. - Sadulla Shaik; Satish Kanapala; Vallabhuni Vijay; Chandra Shaker Pittala (Int. J. Syst. Assur. Eng. Manag., 2023)

State of the art design of adder modules: performance validation of GDI methodology for energy harvesting applications. - Puli Raju; Vallabhuni Vijay; P. Ashok Babu; P. Sridhar (Int. J. Syst. Assur. Eng. Manag., 2023)

1-bit full adder design using next generation semiconductor devices and performance benchmarking at low supply voltages. - S. Lakshmanachari; Sadulla Shaik; G. S. R. Satyanarayana; Inapudi Vasavi; Vallabhuni Vijay; Chandra Shaker Pittala (Int. J. Syst. Assur. Eng. Manag., 2024)

State-of-art design: data selectors using quantum-dot cellular automata. - Menda Sreevani; Vallabhuni Vijay; Kancharapu Chaitanya; Chelle Radhika; Nandi Manjula; D. Radha Krishna Koushik; B. Sai Venumadhav; T. Sai Jaideep; Chandra Shaker Pittala; Sadulla Shaik (Int. J. Syst. Assur. Eng. Manag., 2024)

Design and analysis of a novel compact quaternary adder. - S. Lakshmanachari; Sadulla Shaik; G. S. R. Satyanarayana; Vallabhuni Vijay; Chandra Shaker Pittala; K. Indira; S. Swathi (Int. J. Syst. Assur. Eng. Manag., 2024)