A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational Circuits. - Valmiki Mukherjee; Saraju P. Mohanty; Elias Kougianos (ICCD, 2005)

Reduction of Direct Tunneling Power Dissipation during Behavioral Synthesis of Nanometer CMOS Circuits. - Saraju P. Mohanty; Ramakrishna Velagapudi; Valmiki Mukherjee; Hao Li (ISVLSI, 2005)

Scheduling and binding for low gate leakage nanoCMOS datapath circuit synthesis. - Saraju P. Mohanty; Elias Kougianos; Ramakrishna Velagapudi; Valmiki Mukherjee (ISCAS, 2006)