Delay Fault Test Generation with Cellular Automata. - Sukumar Nandi; Vamsi Boppana; Supratik Chakraborty; Parimal Pal Chaudhuri; Samir Roy (VLSI Design, 1993)

Fault dictionary compaction by output sequence removal. - Vamsi Boppana; W. Kent Fuchs (ICCAD, 1994)

A CAD Tool for Design of On-Chip Store & Generate Scheme. - Sukumar Nandi; Vamsi Boppana; Parimal Pal Chaudhuri (VLSI Design, 1994)

A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. - Vamsi Boppana; Prashant Saxena; Prithviraj Banerjee; W. Kent Fuchs; C. L. Liu 001 (Euro-Par, Vol. I, 1996)

Fault Diagnosis Using State Information. - Vamsi Boppana; Ismed Hartanto; W. Kent Fuchs (FTCS, 1996)

Integrated fault diagnosis targeting reduced simulation. - Vamsi Boppana; W. Kent Fuchs (ICCAD, 1996)

Identification of unsettable flip-flops for partial scan and faster ATPG. - Ismed Hartanto; Vamsi Boppana; W. Kent Fuchs (ICCAD, 1996)

Partial Scan Design Based on State Transition Modeling. - Vamsi Boppana; W. Kent Fuchs (ITC, 1996)

Diagnostic Fault Equivalence Identification Using Redundancy Information and Structural Analysis. - Ismed Hartanto; Vamsi Boppana; W. Kent Fuchs (ITC, 1996)

Full fault dictionary storage based on labeled tree encoding. - Vamsi Boppana; Ismed Hartanto; W. Kent Fuchs (VTS, 1996)

Characterization and Implicit Identification of Sequential Indistinguishability. - Vamsi Boppana; Ismed Hartanto; W. Kent Fuchs (VLSI Design, 1997)

Diagnostic Test Pattern Generation for Sequential Circuits. - Ismed Hartanto; Vamsi Boppana; Janak H. Patel; W. Kent Fuchs (VTS, 1997)

State Information-Based Solutions for Sequential Circuit Diagnosis and Testing - Vamsi Boppana (1997)

Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits. - Vamsi Boppana; W. Kent Fuchs (ICCAD, 1998)

Modeling the unknown! Towards model-independent fault and error diagnosis. - Vamsi Boppana; Masahiro Fujita (ITC, 1998)

Model Checking Based on Sequential ATPG. - Vamsi Boppana; Sreeranga P. Rajan; Koichiro Takayama; Masahiro Fujita (CAV, 1999)

Multiple Error Diagnosis Based on Xlists. - Vamsi Boppana; Rajarshi Mukherjee; Jawahar Jain; Masahiro Fujita; Pradeep Bollineni (DAC, 1999)

Implication and Evaluation Techniques for Proving Fault Equivalence. - M. Enamul Amyeen; W. Kent Fuchs; Irith Pomeranz; Vamsi Boppana (VTS, 1999)

On the Evaluation of Arbitrary Defect Coverage of Test Sets. - Ankur Jain; Michael S. Hsiao; Vamsi Boppana; Masahiro Fujita (VTS, 1999)

A Technique for Identifying RTL and Gate-Level Correspondences. - Srivaths Ravi 001; Niraj K. Jha; Indradeep Ghosh; Vamsi Boppana (ICCD, 2000)

Hierarchical Error Diagnosis Targeting RTL Circuits. - Vamsi Boppana; Indradeep Ghosh; Rajarshi Mukherjee; Jawahar Jain; Masahiro Fujita (VLSI Design, 2000)

Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator. - Biplab K. Sikdar; Kolin Paul; Gosta Pada Biswas; Parimal Pal Chaudhuri; Vamsi Boppana; Cliff Yang; Sobhan Mukherjee (VLSI Design, 2000)

Testing, Verification, and Diagnosis in the Presence of Unknowns. - Ankur Jain; Vamsi Boppana; Rajarshi Mukherjee; Jawahar Jain; Masahiro Fujita; Michael S. Hsiao (VTS, 2000)

Cellular automata as a built in self test structure. - Biplab K. Sikdar; Debesh K. Das; Vamsi Boppana; Cliff Yang; Sobhan Mukherjee; Parimal Pal Chaudhuri (ASP-DAC, 2001)

Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction. - M. Enamul Amyeen; W. Kent Fuchs; Irith Pomeranz; Vamsi Boppana (VTS, 2001)

Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences. - Srivaths Ravi 001; Indradeep Ghosh; Vamsi Boppana; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Design for Verification at the Register Transfer Level. - Indradeep Ghosh; Krishna Sekar; Vamsi Boppana (ASP-DAC/VLSI Design, 2002)

Fault equivalence identification in combinational circuits using implication and evaluation techniques. - M. Enamul Amyeen; W. Kent Fuchs; Irith Pomeranz; Vamsi Boppana (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Accurate pre-layout estimation of standard cell characteristics. - Hiroaki Yoshida; Kaushik De; Vamsi Boppana (DAC, 2004)

Transistor-Level Optimization of Digital Designs with Flex Cells. - Rob Roy; Debashis Bhattacharya; Vamsi Boppana (Computer, 2005)

Low power chips: a fabless asic perspective. - Shashank Bhonge; Vamsi Boppana (ISLPED, 2008)

Implementing the Best Processor Cores. - Vamsi Boppana; Rahoul Varma; S. Balajee (VLSI Design, 2008)

Xilinx Zynq-7000 EPP: An extensible processing platform family. - Vidya Rajagopalan; Vamsi Boppana; Sandeep Dutta; Brad Taylor; Ralph Wittig (Hot Chips Symposium, 2011)

UltraScale+ MPSoC and FPGA families. - Vamsi Boppana; Sagheer Ahmad; Ilya Ganusov; Vinod Kathail; Vidya Rajagopalan; Ralph Wittig (Hot Chips Symposium, 2015)

A 16-nm Multiprocessing System-on-Chip Field-Programmable Gate Array Platform. - Sagheer Ahmad; Vamsi Boppana; Ilya Ganusov; Vinod Kathail; Vidya Rajagopalan; Ralph Wittig (IEEE Micro, 2016)

Xilinx First 7nm Device: Versal AI Core (VC1902). - Sagheer Ahmad; Sridhar Subramanian; Vamsi Boppana; Shankar Lakka; Fu-Hing Ho; Tomai Knopp; Juanjo Noguera; Gaurav Singh; Ralph Wittig (Hot Chips Symposium, 2019)