Selective operations of multi-pillar SOT-MRAM for high density and low power embedded memories. - Kaiming Cai; Simon Van Beek; Siddharth Rao; K. Fan; M. Gupta; Van D. Nguyen; Ganesh Jayakumar; Giacomo Talmelli; S. Couet; Gouri Sankar Kar (VLSI Technology and Circuits, 2022)

Challenges and targets of MRAM-enabled scaled spintronic logic circuits. - Fanfan Meng; Florin Ciubotaru; S.-Y. Lee; Odysseas Zografos; M. Gupta; Van D. Nguyen; Sebastien Couet; Gouri Sankar Kar; Giovanni De Micheli; Christoph Adelmann; I. Asselberghs (CoRR, 2022)

Extremely Scaled Perpendicular SOT-MRAM Array Integration on 300mm Wafer. - Farrukh Yasin; A. Palomino; A. Kumar; Valerio Pica; Simon Van Beek; Giacomo Talmelli; Van D. Nguyen; Stefan Cosemans; D. Crotti; Kurt Wostyn; Gouri Sankar Kar; Sebastien Couet (VLSI Technology and Circuits, 2024)

Benchmarking of Scaled Majority-Logic-Synthesized Spintronic Circuits Based on Magnetic Tunnel Junction Transducers. - Fanfan Meng; Siang-Yun Lee; Odysseas Zografos; Mohit Gupta 004; Van D. Nguyen; Giovanni De Micheli; Sorin Cotofana; Inge Asselberghs; Christoph Adelmann; Gouri Sankar Kar; Sebastien Couet; Florin Ciubotaru (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)