Instruction Set Design for Elementary Set in Tensilica Xtensa. - Anirudh Ingole; Vanita Agarwal (ICCCNT, 2019)

Modified MD5 algorithm for low end IoT Edge devices. - Viraj Khatri; Vanita Agarwal (ICCCNT, 2019)

Architectural Considerations for Next Generation IoT Processors. - Vanita Agarwal; Rajendrakumar A. Patil; Arunkumar B. Patki (IEEE Syst. J., 2019)

Implementation of Lower and Upper Approximation features of rough set theory on FPGA. - Shubham Tonde; Vanita Agarwal (ICCCNT, 2021)

Two-way Communication: An Integrated System for American Sign Language Recognition and Speech-to-Text Translation. - Chinmay Bhat; Rutuja Rajeshirke; Sanskruti Chude; Vaibhavi Mhaiskar; Vanita Agarwal (ICCCNT, 2023)

Development Of SV UVM Testbench For Verification Of AMBA AXI3 IP Used For Memory Access Application. - Abhishek Sanjeev Chandgaonkar; Vaishali Ingale; Vinay Patil; Vanita Agarwal (ICCCNT, 2023)

Design and Verification of a Cache Coherency Verification IP for AMBA ACE Protocol Using UVM. - Ketki Purushottam Kasaralikar; Vaishali Ingale; Vanita Agarwal; Ashlesha Gokhale (ICCCNT, 2024)

Development of Verification IP for PCI Express 5.0 and its Integration with a Hypothetical Slave Device. - Urvika Nema; Vanita Agarwal; Vaishali Ingale; Ashlesha Gokhale (ICCCNT, 2024)