Radiation-tolerant combinational gates - an implementation based comparison. - Varadan Savulimedu Veeravalli; Andreas Steininger (DDECS, 2012)

Protecting an Asynchronous NoC against Transient Channel Faults. - Syed Rameez Naqvi; Varadan Savulimedu Veeravalli; Andreas Steininger (DSD, 2012)

Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip. - Varadan Savulimedu Veeravalli; Thomas Polzer; Andreas Steininger; Ulrich Schmid 001 (DSD, 2012)

Modular Redundancy in a GALS System Using Asynchronous Recovery Links. - Jakob Lechner; Varadan Savulimedu Veeravalli (ASYNC, 2013)

An infrastructure for accurate characterization of single-event transients in digital circuits. - Varadan Savulimedu Veeravalli; Thomas Polzer; Ulrich Schmid 001; Andreas Steininger; Michael Hofbauer; Kurt Schweiger; Horst Dietrich; Kerstin Schneider-Hornstein; Horst Zimmermann; Kay-Obbe Voss; Bruno Merk; Michael Hajek (Microprocess. Microsystems, 2013)

Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example. - Andreas Steininger; Varadan Savulimedu Veeravalli; Dan Alexandrescu; Enrico Costenaro; Lorena Anghel (ICCD, 2014)

Architecture for monitoring SET propagation in 16-bit Sklansky adder. - Varadan Savulimedu Veeravalli; Andreas Steininger (ISQED, 2014)

Measuring SET pulsewidths in logic gates using digital infrastructure. - Varadan Savulimedu Veeravalli; Andreas Steininger; Ulrich Schmid 001 (ISQED, 2014)

Reliable and Continuous Measurement of SET Pulse Widths. - Varadan Savulimedu Veeravalli; Andreas Steininger (DSD, 2015)

Building reliable systems-on-chip in nanoscale technologies. - Andreas Steininger; Horst Zimmermann; Axel Jantsch; Michael Hofbauer; Ulrich Schmid 001; Kurt Schweiger; Varadan Savulimedu Veeravalli (Elektrotech. Informationstechnik, 2015)

Design and Physical Implementation of a Target ASIC for SET Experiments. - Varadan Savulimedu Veeravalli; Andreas Steininger (DSD, 2016)

Study of a delayed single-event effect in the Muller C-element. - Varadan Savulimedu Veeravalli; Andreas Steininger (ETS, 2016)

A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study. - Marko S. Andjelkovic; Milos Krstic; Rolf Kraemer; Varadan Savulimedu Veeravalli; Andreas Steininger (ATS, 2017)

Setup for an Experimental Study of Radiation Effects in 65nm CMOS. - Bernhard Fritz; Andreas Steininger; Václav Simek; Varadan Savulimedu Veeravalli (DSD, 2017)

A versatile architecture for long-term monitoring of single-event transient durations. - Varadan Savulimedu Veeravalli; Andreas Steininger; Ulrich Schmid 001 (Microprocess. Microsystems, 2017)