Switch-Level Timing Simulation of MOS VLSI Circuits - Vasant B. Rao (1985)

HPEX: A Hierarchical Parasitic Circuit Extractor. - Shun-Lin Su; Vasant B. Rao; Timothy N. Trick (DAC, 1987)

Network Partitioning and Ordering for MOS VLSI Circuits. - Vasant B. Rao; Timothy N. Trick (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

Partitioning issues in circuit simulation on multiprocessors. - David C. Yeh; Vasant B. Rao (ICCAD, 1988)

Multi-Input Fuzzy Inference Engine on a Systolic Array. - MahmMahmoud A. Manzoul; Vasant B. Rao (IEA/AIE (Vol. 2), 1988)

An Evolution-Based Approach to Partitioning ASIC Systems. - Youssef Saab; Vasant B. Rao (DAC, 1989)

A Stochastic Algorithm for Circuit Bi-Partitioning. - Youssef Saab; Vasant B. Rao (Great Lakes Computer Science Conference, 1989)

Stochastic Evolution: a Fast Effective Heuristic for Some Generic Layout Problems. - Youssef Saab; Vasant B. Rao (DAC, 1990)

Fast effective heuristics for the graph bisectioning problem. - Youssef Saab; Vasant B. Rao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Rank reduction in graph partitioning. - K. S. Arun; Vasant B. Rao (ICASSP, 1991)

A Convex Optimization Approach to Transistor Sizing for CMOS Circuits. - Sachin S. Sapatnekar; Vasant B. Rao; Pravin M. Vaidya (ICCAD, 1991)

Consistency checking and optimization of macromodels. - Yun-Cheng Ju; Vasant B. Rao; Resve A. Saleh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Combinatorial optimization by stochastic evolution. - Youssef Saab; Vasant B. Rao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

An exact solution to the transistor sizing problem for CMOS circuits using convex optimization. - Sachin S. Sapatnekar; Vasant B. Rao; Pravin M. Vaidya; Sung-Mo Kang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Constructive Heuristics and Lower Bounds for Graph Partitioning Based on a Principal-Components Approximation. - K. S. Arun; Vasant B. Rao (SIAM J. Matrix Anal. Appl., 1993)

On the Convergence of Reversible Markov Chains. - Madhav P. Desai; Vasant B. Rao (SIAM J. Matrix Anal. Appl., 1993)

A characterization of the smallest eigenvalue of a graph. - Madhav P. Desai; Vasant B. Rao (J. Graph Theory, 1994)

Delay Analysis of the Distributed RC Line. - Vasant B. Rao (DAC, 1995)

Design planning for high-performance ASICs. - John Y. Sayah; Rajesh Gupta; Deepak D. Sherlekar; Philip S. Honsinger; Jitendra M. Apte; S. Wayne Bollinger; Hai Hsia Chen; Sumit DasGupta; Edward P. Hsieh; Andrew D. Huber; Edward J. Hughes; Zahi M. Kurzum; et al. (IBM J. Res. Dev., 1996)

Aggressive crunching of extracted RC netlists. - Vasant B. Rao; Jeffrey Soreff; Ravichander Ledalla; Fred L. Yang (Timing Issues in the Specification and Synthesis of Digital Systems, 2002)

Design methodology for the IBM POWER7 microprocessor. - Joshua Friedrich; Ruchir Puri; Uwe Brandt; Markus Bühler; Jack DiLullo; Jeremy Hopkins; Mozammel Hossain; Michael A. Kazda; Joachim Keinert; Zahi M. Kurzum; Douglass Lamb; Alice Lee; et al. (IBM J. Res. Dev., 2011)