An Approach to Implementing Maturity Models in IT Security. - Vasant Rao; Rodger Jamieson (ACIS, 2003)

Transistor-Level Tools for High-End Processor Custom Circuit Design at IBM. - Karen Bard; Bill Dewey; Mei-Ting Hsu; Tom Mitchell 003; Karl Moody; Vasant Rao; Ron Rose; Jeff Soreff; Steve Washburn (Proc. IEEE, 2007)

Statistical path tracing in timing graphs. - Vasant Rao; Debjit Sinha; Nitin Srimal; Prabhat K. Maurya (DAC, 2016)

Statistical Timing Analysis considering Multiple-Input Switching. - Debjit Sinha; Vasant Rao; Chaitanya Peddawad; Michael H. Wood; Jeffrey G. Hemmett; Suriya Skariah; Patrick Williams (DAC, 2020)