Temporal and System Level Modifications for High Speed VLSI Implementations of Cryptographic Core. - Harris E. Michail; Athanasios P. Kakarountas; Athanasios Milidonis; George A. Panagiotakopoulos; Vasilis N. Thanasoulis; Costas E. Goutis (ICECS, 2006)

Server side hashing core exceeding 3 Gbps of throughput. - Harris E. Michail; George A. Panagiotakopoulos; Vasilis N. Thanasoulis; Athanasios Kakarountas; Costas E. Goutis (Int. J. Secur. Networks, 2007)

Dedicated FPGA communication architecture and design for a large-scale neuromorphic system. - Vasilis N. Thanasoulis; Johannes Partzsch; Stephan Hartmann 002; Christian Mayr 001; René Schüffny (ICECS, 2012)

Long-term pulse stimulation and recording in an accelerated neuromorphic system. - Vasilis N. Thanasoulis; Johannes Partzsch; Bernhard Vogginger; Christian Mayr 001; René Schüffny (ICECS, 2012)

Configurable pulse routing architecture for accelerated multi-node neuromorphic systems. - Vasilis N. Thanasoulis; Johannes Partzsch; Bernhard Vogginger; René Schüffny (ICECS, 2014)

A pulse communication flow ready for accelerated neuromorphic experiments. - Vasilis N. Thanasoulis; Bernhard Vogginger; Johannes Partzsch; René Schüffny (ISCAS, 2014)

Neuromorphic hardware in the loop: Training a deep spiking network on the BrainScaleS wafer-scale system. - Sebastian Schmitt; Johann Klähn; Guillaume Bellec; Andreas Grübl; Maurice Güttler; Andreas Hartel; Stephan Hartmann 002; Dan Husmann de Oliveira; Kai Husmann; Sebastian Jeltsch; Vitali Karasenko; Mitja Kleider; et al. (IJCNN, 2017)

Pattern representation and recognition with accelerated analog neuromorphic systems. - Mihai A. Petrovici; Sebastian Schmitt; Johann Klähn; Robert D. St. Louis; Anna Schroeder; Guillaume Bellec; Johannes Bill; Oliver Breitwieser; Ilja Bytschok; Andreas Grübl; Maurice Güttler; Andreas Hartel; et al. (ISCAS, 2017)

Pattern representation and recognition with accelerated analog neuromorphic systems. - Mihai A. Petrovici; Sebastian Schmitt; Johann Klähn; David Stöckel; Anna Schroeder; Guillaume Bellec; Johannes Bill; Oliver Breitwieser; Ilja Bytschok; Andreas Grübl; Maurice Güttler; Andreas Hartel; et al. (CoRR, 2017)

Delay-Based Neural Computation: Pulse Routing Architecture and Benchmark Application in FPGA. - Vasilis N. Thanasoulis; Bernhard Vogginger; Johannes Partzsch; Christian Mayr 001 (ICECS, 2021)