Systematic development of architectures for multidimensional DSP using the residue number system. - Dimitrios Soudris; Vassilis Paliouras; Thanos Stouraitis (ICASSP, 1992)

Systematic design of full adder-based architectures for convolution. - Dimitrios Soudris; Vassilis Paliouras; Thanos Stouraitis; Alexander Skavantzos; Constantinos E. Goutis (ICASSP (1), 1993)

Methodology for the Design of Signed-digit DSP Processors. - Vassilis Paliouras; Dimitrios Soudris; Thanos Stouraitis (ISCAS, 1993)

Systematic Design of Multi-Modulus/Multi-Function Residue Number System Processors. - Vassilis Paliouras; Thanos Stouraitis (ISCAS, 1994)

A Novel Algorithm for Multi-Operand Logarithmic Number System Addition and Subtraction Using Polynominal Approximation. - I. Orginos; Vassilis Paliouras; Thanos Stouraitis (ISCAS, 1995)

Efficient algorithms and VLSI architectures for trigonometric functions in the logarithmic number system based on the subtraction function. - E. N. Malamas; Vassilis Paliouras; Thanos Stouraitis (ICECS, 1996)

Area-time performance of VLSI FIR filter architectures based on residue arithmetic. - Vassilis Paliouras; Thanos Stouraitis (EUROMICRO, 1997)

An operation-saving VLSI geometry engine core. - Konstantina Karagianni; George Diamantakos; Vassilis Paliouras; Thanos Stouraitis (ICASSP, 1997)

A very-long instruction word digital signal processor based on the logarithmic number system. - Vassilis Paliouras; J. Karagiannis; G. Aggouras; Thanos Stouraitis (ICECS, 1998)

A VLSI architecture for fast and accurate floating-point sine/cosine evaluation. - Vassilis Paliouras; Konstantina Karagianni; Thanos Stouraitis (ICECS, 1998)

Novel high-radix residue number system multipliers and adders. - Vassilis Paliouras; Thanos Stouraitis (ISCAS (1), 1999)

High-radix residue number system forward and inverse converters. - Vassilis Paliouras; Thanos Stouraitis (ICECS, 2000)

Logarithmic Number System for Low-Power Arithmetic. - Vassilis Paliouras; Thanos Stouraitis (PATMOS, 2000)

Low-Power Properties of the Logarithmic Number System. - Vassilis Paliouras; Thanos Stouraitis (IEEE Symposium on Computer Arithmetic, 2001)

VLSI architectures for blind equalization based on fractional-order statistics. - Vassilis Paliouras; J. Dagres; Panagiotis Tsakalides; Thanos Stouraitis (ICECS, 2001)

Signal activity and power consumption reduction using the logarithmic number system. - Vassilis Paliouras; Thanos Stouraitis (ISCAS (2), 2001)

Operation-Saving VLSI Architectures for 3D Geometrical Transformations. - Konstantina Karagianni; Vassilis Paliouras; George Diamantakos; Thanos Stouraitis (IEEE Trans. Computers, 2001)

Multi-voltage low power convolvers using the polynomial residue number system. - Vassilis Paliouras; Alexander Skavantzos; Thanos Stouraitis (ACM Great Lakes Symposium on VLSI, 2002)

High-radix modulo rn - 1 multipliers and adders. - Ioannis Kouretas; Vassilis Paliouras (ICECS, 2002)

A computational technique and a VLSI architecture for digital pulse shaping in OFDM modems. - Eleni Fotopoulou; Vassilis Paliouras; Thanos Stouraitis (ISCAS (2), 2003)

High-radix redundant circuits for RNS modulo rn-1, rn, or rn+1. - Ioannis Kouretas; Vassilis Paliouras (ISCAS (5), 2003)

An efficient computational method and a VLSI architecture for digital filtering of CP-OFDM signals. - Eleni Fotopoulou; Vassilis Paliouras (GLOBECOM, 2004)

An efficient architecture for peak-to-average power ratio reduction in OFDM systems in the presence of pulse-shaping filtering. - Theodoros Giannopoulos; Vassilis Paliouras (ISCAS (4), 2004)

An efficient memory compression scheme for 8 k FFT in a DVB-T receiver and the corresponding error model. - Stamatis Krommydas; Vassilis Paliouras (ISCAS (4), 2004)

Optimal Logarithmic Representation in Terms of SNR Behavior. - Panagiotis D. Vouzis; Vassilis Paliouras (PATMOS, 2004)

A novel architecture and a systematic graph-based optimization methodology for modulo multiplication. - Giorgos Dimitrakopoulos; Vassilis Paliouras (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

Using CLNS for FFTs in OFDM demodulation of UWB receivers. - Panagiotis D. Vouzis; Mark G. Arnold; Vassilis Paliouras (ISCAS (4), 2005)

Low-Power VLSI Architectures for OFDM Transmitters Based on PAPR Reduction. - Theodoros Giannopoulos; Vassilis Paliouras (PATMOS, 2005)

Low-Power Aspects of Nonlinear Signal Processing. - Konstantina Karagianni; Vassilis Paliouras (PATMOS, 2005)

Novel efficient weighting factors for PTS-based PAPR reduction in low-power OFDM transmitters. - Theodoros Giannopoulos; Vassilis Paliouras (EUSIPCO, 2006)

A novel technique for low-power D/A conversion based on PAPR reduction. - Theodoros Giannopoulos; Vassilis Paliouras (ISCAS, 2006)

Low-Power Maximum Magnitude Computation for PAPR Reduction in OFDM Transmitters. - Theodoros Giannopoulos; Vassilis Paliouras (PATMOS, 2006)

Simplified Criteria for Early Iterative Decoding Termination. - Spyros Gidaros; Vassilis Paliouras (SiPS, 2006)

Low-Power Saturated Arithmetic and its Application in VLSI Architectures for OFDM Modems. - Konstantina Karagianni; Vassilis Paliouras; Theodoros Giannopoulos (SiPS, 2006)

Editorial. - Johan Vounckx; Vassilis Paliouras (J. Low Power Electron., 2006)

Low-Power Digital Filtering Based on the Logarithmic Number System. - Charalambos Basetas; Ioannis Kouretas; Vassilis Paliouras (PATMOS, 2007)

On The Complexity of Joint Demodulation and Convolutional Decoding. - Dimitris Gkrimpas; Vassilis Paliouras (SiPS, 2007)

On the implementation of bus-based architectures for LDPC decoding. - G. Aggouras; Vassilis Paliouras (ISWPC, 2008)

A frequency-domain interpolation implementation for OFDM transmitters. - Eleni Fotopoulou; Vassilis Paliouras; Thanos Stouraitis (ISWPC, 2008)

Relationship among BER, power consumption and PAPR. - Theodoros Giannopoulos; Vassilis Paliouras (ISWPC, 2008)

Impact of roundoff errors in LDPC decoding. - Nikos Kanistras; Vassilis Paliouras (ISWPC, 2008)

Roundoff error effects on a Quasi-Newton frequency domain channel equalizer. - Panos Karaivazoglou; Konstantina Karagianni; Vassilis Paliouras; Kostas Berberidis (ISWPC, 2008)

Packet detector for multiband UWB. - D. Pettas; Vassilis Paliouras (ISWPC, 2008)

Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication. - Ioannis Kouretas; Vassilis Paliouras (PATMOS, 2008)

Impact of roundoff error on the decisions of the Log Sum-Product algorithm for LDPC decoding. - Nikos Kanistras; Vassilis Paliouras (SiPS, 2008)

Variation-tolerant Design Using Residue Number System. - Ioannis Kouretas; Vassilis Paliouras (DSD, 2009)

High-radix residue arithmetic bases for low-power DSP systems. - Ioannis Kouretas; Vassilis Paliouras (DPS, 2009)

Residue Arithmetic for Variation-Tolerant Design of Multiply-Add Units. - Ioannis Kouretas; Vassilis Paliouras (PATMOS, 2009)

A Low-Complexity High-Radix RNS Multiplier. - Ioannis Kouretas; Vassilis Paliouras (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A Low-Complexity PTS-based PAPR Reduction Technique for OFDM Signals without Transmission of Side Information. - Theodoros Giannopoulos; Vassilis Paliouras (J. Signal Process. Syst., 2009)

RNS multi-voltage low-power multiply-add unit. - Ioannis Kouretas; Vassilis Paliouras (ICECS, 2010)

VLSI implementation and performance of turbo decoding stopping criteria. - Angelos Spanos; Vassilis Paliouras (ICECS, 2010)

Residue arithmetic bases for reducing delay variation. - Ioannis Kouretas; Vassilis Paliouras (ISCAS, 2010)

Residue Arithmetic for Designing Low-Power Multiply-Add Units. - Ioannis Kouretas; Vassilis Paliouras (PATMOS, 2010)

Towards a Quaternion Complex Logarithmic Number System. - Mark G. Arnold; John R. Cowles; Vassilis Paliouras; Ioannis Kouretas (IEEE Symposium on Computer Arithmetic, 2011)

A Residue Logarithmic Number System ALU using interpolation and cotransformation. - Mark G. Arnold; Ioannis Kouretas; Vassilis Paliouras (ASAP, 2011)

A flexible high-throughput hardware architecture for a gaussian noise generator. - Ioannis Paraskevakos; Vassilis Paliouras (ICASSP, 2011)

A syndrome-based LDPC decoder with very low error floor. - Ioannis Tsatsaragkos; Nikos Kanistras; Vassilis Paliouras (DSP, 2011)

Multiple LDPC decoder of very low bit-error rate. - Ioannis Tsatsaragkos; Nikos Kanistras; Vassilis Paliouras (DSP, 2011)

Digital baseband challenges for a 60GHz gigabit link. - Nikos Kanistras; Ioannis Tsatsaragkos; Ahmed Mahdi; Konstantina Karagianni; Vassilis Paliouras; Fotios Gioulekas; E. Lalos; Kostas Adaos; Michael K. Birbas; Panos Karaivazoglou; M. V. Koziotis; M. Perakis (ICECS, 2011)

Next generation millimeter wave backhaul radio: Overall system design for GbE 60GHz PtP wireless radio of high CMOS integration. - Rodoula Makri; Petros Tsenes; Dimitrios Economou; Yannis Papananos; Dimitrios Dervenis; Michael K. Birbas; John C. Kikidis; Vassilis Paliouras; Grigorios Kalivas; Alexios N. Birbas; Panos Karaivazoglou; Yorgos Stratakos; et al. (ICECS, 2011)

On the impact of encoding on the complexity of residue arithmetic circuits. - E. Theodorakis; Vassilis Paliouras (ICECS, 2011)

A flexible layered LDPC decoder. - Ioannis Tsatsaragkos; Vassilis Paliouras (ISWCS, 2011)

Using the arithmetic representation properties of data to reduce the area and power consumption of FFT circuits for wireless OFDM systems. - Andreas Brokalakis; Vassilis Paliouras (SiPS, 2011)

An encoding scheme and encoder architecture for rate-compatible QC-LDPC codes. - Ahmed Mahdi; Nikos Kanistras; Vassilis Paliouras (SiPS, 2011)

Impact of Approximation Error on the Decisions of LDPC Decoding. - Nikos Kanistras; Vassilis Paliouras (J. Signal Process. Syst., 2011)

Hardware design and verification techniques for Giga-bit Forward-Error Correction systems on FPGAs. - Ahmed Mahdi; Panagiotis Sakellariou; Nikos Kanistras; Ioannis Tsatsaragkos; Vassilis Paliouras (ICECS, 2012)

Low-power two's-complement multiplication based on selective activation. - Panagiotis Sakellariou; Vassilis Paliouras (ICECS, 2012)

Residue arithmetic for designing multiply-add units in the presence of non-gaussian variation. - Ioannis Kouretas; Vassilis Paliouras (ISCAS, 2012)

Low-Power Delay Sensors on FPGAs. - Panagiotis Sakellariou; Vassilis Paliouras (PATMOS, 2012)

An FPGA-based prototyping method for verification, characterization and optimization of LDPC error correction systems. - Panagiotis Sakellariou; Ioannis Tsatsaragkos; Nikos Kanistras; Ahmed Mahdi; Vassilis Paliouras (ICSAMOS, 2012)

Propagation of LLR Saturation and Quantization Error in LDPC Min-Sum Iterative Decoding. - Nikos Kanistras; Ioannis Tsatsaragkos; Vassilis Paliouras (SiPS, 2012)

Simplified Multi-Level Quasi-Cyclic LDPC Codes for Low-Complexity Encoders. - Ahmed Mahdi; Vassilis Paliouras (SiPS, 2012)

Error Floor Compensation for LDPC Codes Using Concatenated Schemes. - G. Spourlis; Ioannis Tsatsaragkos; Nikos Kanistras; Vassilis Paliouras (SiPS, 2012)

Delay-variation-tolerant FIR filter architectures based on the Residue Number System. - Ioannis Kouretas; Vassilis Paliouras (ISCAS, 2013)

A semi-analytical bivariate Gaussian model of the approximation error impact on the Min-Sum LDPC decoding algorithm. - Nikos Kanistras; Vassilis Paliouras (SiPS, 2013)

Low-Power Logarithmic Number System Addition/Subtraction and Their Impact on Digital Filters. - Ioannis Kouretas; Charalambos Basetas; Vassilis Paliouras (IEEE Trans. Computers, 2013)

Effective sum of squares implementation for BPSK soft-decision decoding. - P. Mermigkas; Vassilis Paliouras (ICECS, 2014)

A technique for the identification of trapping sets in LDPC codes. - Christos Vasilopoulos; Vassilis Paliouras (ICECS, 2014)

A Low Complexity-High Throughput QC-LDPC Encoder. - Ahmed Mahdi; Vassilis Paliouras (IEEE Trans. Signal Process., 2014)

Approximate Algorithms for Identifying Minima on Min-Sum LDPC Decoders and Their Hardware Implementation. - Ioannis Tsatsaragkos; Vassilis Paliouras (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

On the Encoding Complexity of Quasi-Cyclic LDPC Codes. - Ahmed Mahdi; Vassilis Paliouras (IEEE Trans. Signal Process., 2015)

Dynamic delay variation behaviour of RNS multiply-add architectures. - Kleanthis Papachatzopoulos; Ioannis Kouretas; Vassilis Paliouras (ISCAS, 2016)

Application-Specific Low-Power Multipliers. - Panagiotis Sakellariou; Vassilis Paliouras (IEEE Trans. Computers, 2016)

Work in progress: An introduction to computing course using a Python-based experiential approach. - Nikolaos M. Avouris; Kyriakos N. Sgarbas; Vassilis Paliouras; Michalis Koukias (EDUCON, 2017)

An approximate hardware check node for λ-min-based LDPC decoders. - Georgios Perris-Samios; Vassilis Paliouras (EUSIPCO, 2017)

Logarithmic number system addition-subtraction using fractional normalization. - Giorgos Tsiaras; Vassilis Paliouras (ISCAS, 2017)

Hardware trade-offs for massive MIMO uplink detection based on Newton iteration method. - Alexios Thanos; Vassilis Paliouras (MOCAST, 2017)

Multi-operand logarithmic addition/subtraction based on Fractional Normalization. - Giorgos Tsiaras; Vassilis Paliouras (MOCAST, 2017)

Simplified Deep-Learning-based decoders for linear block codes. - Emmanouil Kavvousanos; Vassilis Paliouras; Ioannis Kouretas (ICECS, 2018)

Hardware aspects of Long Short Term Memory. - Ioannis Kouretas; Vassilis Paliouras (ICECS, 2018)

Data representation and hardware aspects in a fully-folded successive-cancellation polar decoder. - Christos Andriakopoulos; Vassilis Paliouras (MOCAST, 2018)

A novel algorithm and hardware architecture for low-complexity soft demappers. - Andreas Kalampoukas; Vassilis Paliouras (MOCAST, 2018)

Logarithmic number system for deep learning. - Ioannis Kouretas; Vassilis Paliouras (MOCAST, 2018)

Low-cost soft-error compensation for transposed FIR digital filters. - Vassilis Paliouras; Konstantina Karagianni; Yann Oster (MOCAST, 2018)

Quantitative Evaluation of Certain SET Mitigation Techniques for Multiply-Accumulate Circuits and State Machines. - Vassilis Paliouras; Konstantina Karagianni; Yann Oster (PATMOS, 2018)

Low-Power Addition With Borrow-Save Adders Under Threshold Voltage Variability. - Kleanthis Papachatzopoulos; Vassilis Paliouras (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Reconfigurable RO-Path Delay Sensor. - Panagiotis Sakellariou; Vassilis Paliouras (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Reconfigurable LDPC Decoder Optimized for 802.11n/ac Applications. - Ioannis Tsatsaragkos; Vassilis Paliouras (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Under- and Overflow Detection in the Residue Logarithmic Number System. - Mark G. Arnold; Ioannis Kouretas; Vassilis Paliouras; John R. Cowles (ARITH, 2019)

Versatile Hardware Generation of alpha-Stable Noise for PLC Channel Emulation. - Konstantina Karagianni; Vassilis Paliouras (ICECS, 2019)

Simplified Hardware Implementation of the Softmax Activation Function. - Ioannis Kouretas; Vassilis Paliouras (MOCAST, 2019)

Hardware Implementation Aspects of a Syndrome-based Neural Network Decoder for BCH Codes. - Emmanouil Kavvousanos; Vassilis Paliouras (NORCAS, 2019)

Sphere Decoder for Massive MIMO Systems. - Dimitris Vordonis; Vassilis Paliouras (NORCAS, 2019)

One-Hot Residue Logarithmic Number Systems. - Mark G. Arnold; Ioannis Kouretas; Vassilis Paliouras; Austin Morgan (PATMOS, 2019)

Radix-3 low-complexity modulo-M multipliers. - Ioannis Kouretas; Vassilis Paliouras (PATMOS, 2019)

Static Delay Variation Models for Ripple-Carry and Borrow-Save Adders. - Kleanthis Papachatzopoulos; Vassilis Paliouras (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Maximum Delay Models for Parallel-Prefix Adders in the Presence of Threshold Voltage Variations. - Kleanthis Papachatzopoulos; Vassilis Paliouras (ARITH, 2020)

An Iterative Approach to Syndrome-based Deep Learning Decoding. - Emmanouil Kavvousanos; Vassilis Paliouras (GLOBECOM (Workshops), 2020)

Approximate Sorting Check Node Processing in Non-Binary LDPC Decoders. - Dimitris Chytas; Vassilis Paliouras (ICECS, 2020)

Novel Noise-Shaping Stochastic-Computing Converters for Digital Filtering. - Kleanthis Papachatzopoulos; Chris Andriakopoulos; Vassilis Paliouras (ISCAS, 2020)

Implementing the Residue Logarithmic Number System Using Interpolation and Cotransformation. - Mark G. Arnold; Vassilis Paliouras; Ioannis Kouretas (IEEE Trans. Computers, 2020)

Optimizing Deep Learning Decoders for FPGA Implementation. - Emmanouil Kavvousanos; Vassilis Paliouras (FPL, 2021)

A 5G-code based iterative Non-Binary LDPC decoder. - Dimitris Chytas; Vassilis Paliouras (ICECS, 2021)

On Reducing the Number of Multiplications in RNS-based CNN Accelerators. - Vasilis Sakellariou; Vassilis Paliouras; Ioannis Kouretas; Hani H. Saleh; Thanos Stouraitis (ICECS, 2021)

A Novel Stochastic Polar Architecture for All-Digital Transmission. - Chris Andriakopoulos; Kleanthis Papachatzopoulos; Vassilis Paliouras (ISCAS, 2021)

Simplified Hardware Implementation of Memoryless Dot Product for Neural Network Inference. - Ioannis Kouretas; Vassilis Paliouras (ISCAS, 2021)

An FPGA Accelerator for Spiking Neural Network Simulation and Training. - Vasilis Sakellariou; Vassilis Paliouras (ISCAS, 2021)

Hardware Aspects of Parallel Neural Network Implementation. - Ioannis Kouretas; Vassilis Paliouras (MOCAST, 2021)

High-Level Synthesis design approach for Number-Theoretic Transform Implementations. - Alexander El-Kady; Apostolos P. Fournaris; Thanasis Tsakoulis; Evangelos Haleplidis; Vassilis Paliouras (VLSI-SoC, 2021)

Hardware Implementation and Performance Analysis of Improved Sphere Decoder in Spatially Correlated Massive MIMO Channels. - Dimitris Vordonis; Vassilis Paliouras (IEEE Open J. Commun. Soc., 2021)

Sum Propagate Adders. - Giorgos Dimitrakopoulos; Kleanthis Papachatzopoulos; Vassilis Paliouras (IEEE Trans. Emerg. Top. Comput., 2021)

A Multirate Fully Parallel LDPC Encoder for the IEEE 802.11n/ac/ax QC-LDPC Codes Based on Reduced Complexity XOR Trees. - Ahmed Mahdi; Nikos Kanistras; Vassilis Paliouras (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Sensitivity to Threshold Voltage Variations of Exact and Incomplete Prefix Addition Trees. - Kleanthis Papachatzopoulos; Vassilis Paliouras (ISCAS, 2022)

A High-performance RNS LSTM block. - Vasilis Sakellariou; Vassilis Paliouras; Ioannis Kouretas; Hani H. Saleh; Thanos Stouraitis (ISCAS, 2022)

A Low-Latency Syndrome-based Deep Learning Decoder Architecture and its FPGA Implementation. - Emmanouil Kavvousanos; Vassilis Paliouras (MOCAST, 2022)

Hardware Aspects of Iterative Receivers for V2X Applications. - Thodoris Spanos; Vassilis Paliouras (MOCAST, 2022)

Reconfigurable Intelligent Surface-Aided OFDM Wireless Communications: Hardware Aspects of Reflection Optimization Methods. - Dimitris Vordonis; Dimitris Kompostiotis; Vassilis Paliouras (MOCAST, 2022)

High-Level Synthesis design approach for Number-Theoretic Multiplier. - Alexander El-Kady; Apostolos P. Fournaris; Evangelos Haleplidis; Vassilis Paliouras (VLSI-SoC, 2022)

Modified Logarithmic Multiplication Approximation for Machine Learning. - Ioannis Kouretas; Vassilis Paliouras; Thanos Stouraitis (AICAS, 2023)

Improving Residue-Level Sparsity in RNS-based Neural Network Hardware Accelerators via Regularization. - Emmanouil Kavvousanos; Vasilis Sakellariou; Ioannis Kouretas; Vassilis Paliouras; Thanos Stouraitis (ARITH, 2023)

Received Power Maximization with Practical Phase-Dependent Amplitude Response in RIS-Aided OFDM Wireless Communications. - Dimitris Kompostiotis; Dimitris Vordonis; Vassilis Paliouras (ICASSP, 2023)

Secrecy Rate Maximization in RIS-Enabled OFDM Wireless Communications: The Circuit-Based Reflection Model Case. - Dimitris Kompostiotis; Dimitris Vordonis; Vassilis Paliouras; George C. Alexandropoulos (ICC Workshops, 2023)

Invited Paper: Dilithium Hardware-Accelerated Application Using OpenCL-Based High-Level Synthesis. - Alexander El-Kady; Apostolos P. Fournaris; Vassilis Paliouras (ICCAD, 2023)

A Regularization Approach to Maximize Common Sub-Expressions in Neural Network Weights. - Emmanouil Kavvousanos; Ioannis Kouretas; Vassilis Paliouras; Thanos Stouraitis (ICECS, 2023)

Path-Based Delay Variation Models for Parallel-Prefix Adders. - Kleanthis Papachatzopoulos; Vassilis Paliouras (IEEE Trans. Emerg. Top. Comput., 2023)

Noise-Shaping Binary-to-Stochastic Converters for Reduced-Length Bit-Streams. - Kleanthis Papachatzopoulos; Vassilis Paliouras (IEEE Trans. Emerg. Top. Comput., 2023)

An end-to-end RNS CNN Accelerator. - Vasilis Sakellariou; Vassilis Paliouras; Ioannis Kouretas; Hani H. Saleh; Thanos Stouraitis (AICAS, 2024)

SECURED for Health: Scaling Up Privacy to Enable the Integration of the European Health Data Space. - Francesco Regazzoni 001; Gergely Ács; Albert Zoltan Aszalos; Christos Avgerinos; Nikolaos Bakalos; Josep Lluis Berral; Joppe W. Bos; Marco Brohet; Andrés G. Castillo Sanz; Gareth T. Davies; Stefanos Florescu; Pierre-Elisée Flory; et al. (DATE, 2024)

Secrecy Rate Maximization in MIMO RIS-Aided Wireless Communications: A Hardware Accelerator Implementation for Reflection Optimization. - Dimitris Kompostiotis; Vassilis Paliouras (SiPS, 2024)

Angle of Arrival Estimation Using SRS in 5G NR Uplink Scenarios. - Thodoris Spanos; Fran Fabra; José A. Lopez-Salcedo; Gonzalo Seco-Granados; Nikos Kanistras; Ivan Lapin; Vassilis Paliouras (WIPHAL, 2024)

Evaluation of RIS-Enabled B5G/6G Indoor Positioning and Mapping using Ray Tracing Models. - Dimitris Kompostiotis; Dimitris Vordonis; Vassilis Paliouras; George C. Alexandropoulos; Florin Grec (CoRR, 2024)

USRP-Based Single Anchor Positioning: AoA with 5G Uplink Signals, and UWB Ranging. - Thodoris Spanos; Fran Fabra; José A. Lopez-Salcedo; Gonzalo Seco-Granados; Nikos Kanistras; Ivan Lapin; Vassilis Paliouras (CoRR, 2024)

A Multiplier-Free RNS-Based CNN Accelerator Exploiting Bit-Level Sparsity. - Vasilis Sakellariou; Vassilis Paliouras; Ioannis Kouretas; Hani H. Saleh; Thanos Stouraitis (IEEE Trans. Emerg. Top. Comput., 2024)

Novel Scheduling and Shifter Networks for 5G LDPC Decoders. - Nikos Papageorgiou; Vassilis Paliouras (DASIP, 2025)

A Mixed-Precision RNS DNN Accelerator. - Vasilis Sakellariou; Vassilis Paliouras; Ioannis Kouretas; Hani H. Saleh; Thanos Stouraitis (ISCAS, 2025)

Evaluating Beam Sweeping for AoA Estimation with an RIS Prototype: Indoor/Outdoor Field Trials. - Dimitris Vordonis; Dimitris Kompostiotis; Vassilis Paliouras; George C. Alexandropoulos; Florin Grec (WCNC, 2025)