An Academic RISC-V Silicon Implementation Based on Open-Source Components. - Jaume Abella 001; Calvin Bulla; Guillem Cabo; Francisco J. Cazorla; Adrián Cristal; Max Doblas; Roger Figueras; Alberto González 004; Carles Hernández 001; César Hernández; Víctor Jiménez; Leonidas Kosmidis; et al. (DCIS, 2020)

HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem. - Vatistas Kostalabros; Jordi Ribes-González; Oriol Farràs; Miquel Moretó; Carles Hernández 001 (FPL, 2021)

A Security Model for Randomization-based Protected Caches. - Jordi Ribes-González; Oriol Farràs; Carles Hernández 001; Vatistas Kostalabros; Miquel Moretó (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022)

A Safety-Critical, RISC-V SoC Integrated and ASIC-Ready Classic McEliece Accelerator. - Vatistas Kostalabros; Jordi Ribes-González; Oriol Farràs; Miquel Moretó; Carles Hernández 001 (ARC, 2024)

Hardware Acceleration for High-Volume Operations of CRYSTALS-Kyber and CRYSTALS-Dilithium. - Xavier Carril; Charalampos Kardaris; Jordi Ribes-González; Oriol Farràs; Carles Hernández 001; Vatistas Kostalabros; Joel Ulises González-Jiménez; Miquel Moretó (ACM Trans. Reconfigurable Technol. Syst., 2024)