Material, Process and System Level Analysis for Parasitic Reduction of Next Generation Logic Technology in Conjunction with Backside Power Delivery. - Ashish Pal; Sefa Dag; Pratik B. Vyas; Gregory Costrini; Vinod Reddy; Veeraraghavan Basker; Allen Yeong; Benjamin Colombeau; Bala Haran; Subi Kengeri; El Mehdi Bazizi (VLSI Technology and Circuits, 2024)