Python-based DSL for generating Verilog model of Synchronous Digital Circuits. - Mandar Datar 001; Dhruva S. Hegde; Vendra Durga Prasad; Manish Prajapati; Neralla Manikanta; Devansh Gupta; Janampalli Pavanija; Pratyush Pare; Akash; Shivam Gupta; Sachin B. Patkar (CoRR, 2024)