Simulation Study of III-V Lateral Tunnel FETs with Gate-Drain Underlap. - Venkata Appa Rao Yempada; Srivatsava Jandhyala (VDAT, 2019)

>Optimization of CMOS compatible non-perovskite ferroelectric gate stack for designing low power Ferroelectric tunnel FETs. - Venkata Appa Rao Yempada; Srivatsava Jandhyala; Janamani Chandram Ayyangalam (VDAT, 2024)