1-cycle code decompression circuitry for performance increase of Xtensa-1040-based embedded systems. - Haris Lekatsas; Jörg Henkel; Venkata Jakkula (CICC, 2002)

Design of an one-cycle decompression hardware for performance increase in embedded systems. - Haris Lekatsas; Jörg Henkel; Venkata Jakkula (DAC, 2002)

CoCo: a hardware/software platform for rapid prototyping of code compression technologies. - Haris Lekatsas; Jörg Henkel; Srimat T. Chakradhar; Venkata Jakkula; Murugan Sankaradass (DAC, 2003)

Cypress: Compression and Encryption of Data and Code for Embedded Multimedia Systems. - Haris Lekatsas; Jörg Henkel; Srimat T. Chakradhar; Venkata Jakkula (IEEE Des. Test Comput., 2004)

A Unified Architecture for Adaptive Compression of Data and Code on Embedded Systems. - Haris Lekatsas; Jörg Henkel; Venkata Jakkula; Srimat T. Chakradhar (VLSI Design, 2005)

Chisel: A Storage-efficient, Collision-free Hash-based Network Processing Architecture. - Jahangir Hasan; Srihari Cadambi; Venkata Jakkula; Srimat T. Chakradhar (ISCA, 2006)

Using Shiftable Content Addressable Memories to Double Memory Capacity on Embedded Systems. - Haris Lekatsas; Jörg Henkel; Venkata Jakkula; Srimat T. Chakradhar (VLSI Design, 2006)

A Massively Parallel Digital Learning Processor. - Hans Peter Graf; Srihari Cadambi; Igor Durdanovic; Venkata Jakkula; Murugan Sankaradass; Eric Cosatto; Srimat T. Chakradhar (NIPS, 2008)

A Massively Parallel Coprocessor for Convolutional Neural Networks. - Murugan Sankaradass; Venkata Jakkula; Srihari Cadambi; Srimat T. Chakradhar; Igor Durdanovic; Eric Cosatto; Hans Peter Graf (ASAP, 2009)

A Massively Parallel FPGA-Based Coprocessor for Support Vector Machines. - Srihari Cadambi; Igor Durdanovic; Venkata Jakkula; Murugan Sankaradass; Eric Cosatto; Srimat T. Chakradhar; Hans Peter Graf (FCCM, 2009)

A dynamically configurable coprocessor for convolutional neural networks. - Srimat T. Chakradhar; Murugan Sankaradass; Venkata Jakkula; Srihari Cadambi (ISCA, 2010)