A Novel Constant-pulse Scheme for Synchronous Half-bridge Converter Module. - Oliver Lexter July A. Jose; Venkata Naveen Kolakaluri; Chua-Chin Wang (APCCAS, 2022)

2-Level Miller Detection-Based High Side Gate Driver Design for Power MOSFETs. - Oliver Lexter July A. Jose; Venkata Naveen Kolakaluri; Jui-Min Kuo; Mitch Ming-Chi Chou; Chua-Chin Wang (APCCAS, 2023)

Matrix Phase Shift Based DPWM Technique To Achieve 90% Duty Cycle. - Venkata Naveen Kolakaluri; Oliver Lexter July A. Jose; Chua-Chin Wang (ISCAS, 2023)

SiC MOSFET High Side Gate Driver Design Using HV CMOS Process. - Oliver Lexter July A. Jose; Jui-Min Kuo; Venkata Naveen Kolakaluri; Chua-Chin Wang (MWSCAS, 2023)

A 99.6 % Duty Cycle High-Resolution DPWM Using Reconfiguring Decoder. - Venkata Naveen Kolakaluri; Oliver Lexter July A. Jose; Chua-Chin Wang (MWSCAS, 2023)

Active Gate Driver Design Using Differential Timing-based Miller Detector for Power MOSFET. - Pradyumna Vellanki; Venkata Naveen Kolakaluri; Yun-Che Chang; L. S. S. Pavan Kumar Chodisetti; Mitch Ming-Chi Chou; Chua-Chin Wang (APCCAS, 2024)

A 10-MHz 5-V On-chip 6-layer Multi-level Digital Transformer Using T18HVG2 Process. - Oliver Lexter July A. Jose; Yun-Che Chang; Venkata Naveen Kolakaluri; Celso B. Co; Mitch Ming-Chi Chou; Chua-Chin Wang (ISCAS, 2024)

A Wide Range 2-to-2048 Division Ratio Frequency Divider Using 40-nm CMOS Process. - Soumika Majumder; Venkata Naveen Kolakaluri; Oliver Lexter July A. Jose; Chua-Chin Wang (ISCAS, 2024)

A Multi-Level Power Gating Logic Controlled Driver for A 10-V Power Transistor Using 180-nm High Voltage BCD Process. - Soumika Majumder; Lean Karlo Santos Tolentino; Oliver Lexter July Alvarez Jose; Venkata Naveen Kolakaluri; Mitch Ming-Chi Chou; Chua-Chin Wang (ISOCC, 2024)

A 6.25-MHz 3.4-mW Single Clock DPWM Technique Using Matrix Shift Array. - Oliver Lexter July A. Jose; Venkata Naveen Kolakaluri; Ralph Gerard B. Sangalang; Lean Karlo S. Tolentino; Chua-Chin Wang (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Up To 99.6 % duty cycle digital PWM using 180-nm CMOS process. - Chua-Chin Wang; Oliver Lexter July Alvarez Jose; Venkata Naveen Kolakaluri (Microelectron. J., 2025)