Analysis of Bit Transition Count for EDAC Encoded FSM. - N. Venkateswaran 002; V. Balaji; Venkataraman Mahalingam; T. L. Rajaprabhu (IOLTS, 2003)

Crosstalk Fault Tolerant Processor Architecture - A Power Aware Design. - N. Venkateswaran 002; V. Barath Kumar; R. Raghavan; R. Srinivas; S. Subramanian; V. Balaji; Venkataraman Mahalingam; T. L. Rajaprabhu (DELTA, 2004)

A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection. - Venkataraman Mahalingam; N. Ranganathan (ISVLSI, 2005)

A novel approach for variation aware power minimization during gate sizing. - Venkataraman Mahalingam; N. Ranganathan; Justin E. Harlow III (ISLPED, 2006)

An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition. - Venkataraman Mahalingam; N. Ranganathan (VLSI Design, 2006)

Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition. - Venkataraman Mahalingam; Nagarajan Ranganathan (IEEE Trans. Computers, 2006)

Variation Aware Timing Based Placement Using Fuzzy Programming. - Venkataraman Mahalingam; N. Ranganathan (ISQED, 2007)

Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty. - N. Ranganathan; Upavan Gupta; Venkataraman Mahalingam (ACM Great Lakes Symposium on VLSI, 2008)

A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing. - Venkataraman Mahalingam; Nagarajan Ranganathan (ISVLSI, 2008)

A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing. - Venkataraman Mahalingam; N. Ranganathan; J. E. Harlow (IEEE Trans. Very Large Scale Integr. Syst., 2008)

A VLSI System Architecture for Optical Flow Computation. - Koustav Bhattacharya; Venkataraman Mahalingam; Nagarajan Ranganathan (ISCAS, 2009)

Variation-aware multimetric optimization during gate sizing. - Nagarajan Ranganathan; Upavan Gupta; Venkataraman Mahalingam (ACM Trans. Design Autom. Electr. Syst., 2009)

A VLSI Architecture and Algorithm for Lucas-Kanade-Based Optical Flow Computation. - Venkataraman Mahalingam; Koustav Bhattacharya; N. Ranganathan; Hari Chakravarthula; Robin R. Murphy; Kevin S. Pratt (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Timing-Based Placement Considering Uncertainty Due to Process Variations. - Venkataraman Mahalingam; N. Ranganathan (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Dynamic clock stretching for variation compensation in VLSI circuit design. - Venkataraman Mahalingam; Nagarajan Ranganathan; Ransford Hyman Jr. (ACM J. Emerg. Technol. Comput. Syst., 2012)