Parallel Composition of Lockstep Synchronous Processes for Hardware Validation: Divide-and-Conquer Composition. - Ganesh Gopalakrishnan; Narayana Mani; Venkatesh Akella (Automatic Verification Methods for Finite State Systems, 1989)

HOP: A process model for synchronous hardware; semantics and experiments in process composition. - Ganesh Gopalakrishnan; Richard M. Fujimoto; Venkatesh Akella; Narayana Mani (Integr., 1989)

SHILPA: a high-level synthesis system for self-timed circuits. - Venkatesh Akella; Ganesh Gopalakrishnan (ICCAD, 1992)

From Process-Oriented Functional Specifications to Efficient Asynchronous Circuits. - Venkatesh Akella; Ganesh Gopalakrishnan (VLSI Design, 1992)

VLSI asynchronous systems: specification and synthesis. - Ganesh Gopalakrishnan; Venkatesh Akella (Microprocess. Microsystems, 1992)

A transformational approach to asynchronous high-level synthesis. - Ganesh Gopalakrishnan; Venkatesh Akella (VLSI, 1993)

A technique for estimating power in asynchronous circuits. - Prabhakar Kudva; Venkatesh Akella (ASYNC, 1994)

Performance Analysis and Optimization of Asynchronous Circuits. - Prabhakar Kudva; Ganesh Gopalakrishnan; Erik Brunvand; Venkatesh Akella (ICCD, 1994)

Testing two-phase transition signaling based self-timed circuits in a synthesis environment. - Prabhakar Kudva; Venkatesh Akella (HLSS, 1994)

CFSIM: A Concurrent Compiled Code Functional Simulator for hopCP. - Venkatesh Akella; Ganesh Gopalakrishnan (Int. J. Comput. Simul., 1994)

Specification and Validation of Control-Intensive IC's in hopCP. - Venkatesh Akella; Ganesh Gopalakrishnan (IEEE Trans. Software Eng., 1994)

High-level optimizations in compiling process descriptions to asynchronous circuits. - Ganesh Gopalakrishnan; Venkatesh Akella (J. VLSI Signal Process., 1994)

Asynchronous 2-D discrete cosine transform core processor. - Bret Stott; Dave Johnson 003; Venkatesh Akella (ICCD, 1995)

Counterflow pipeline based dynamic instruction scheduling. - Tony Werner; Venkatesh Akella (ASYNC, 1996)

Limitations of VLSI Implementation of Delay-Insensitive Codes. - Venkatesh Akella; Nitin H. Vaidya; G. Robert Redinbo (FTCS, 1996)

Asynchronous Processor Survey. - Tony Werner; Venkatesh Akella (Computer, 1997)

Asynchronous Comparison-Based Decoders for Delay-Insensitive Codes. - Venkatesh Akella; Nitin H. Vaidya; G. Robert Redinbo (IEEE Trans. Computers, 1998)

Micropipelined asynchronous discrete cosine transform (DCT/IDCT) processor. - Dave Johnson 003; Venkatesh Akella; Bret Stott (IEEE Trans. Very Large Scale Integr. Syst., 1998)

Automatic Insertion of Gated Clocks at Register Transfer Level. - Nithya Raghavan; Venkatesh Akella; Smita Bakshi (VLSI Design, 1999)

An Asynchronous Superscalar Architecture for Exploiting Instruction-Level Parallelism. - Tony Werner; Venkatesh Akella (ASYNC, 2001)

Improving DSP Performance with a Small Amount of Field Programmable Logic. - John Y. Oliver; Venkatesh Akella (FPL, 2003)

Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture. - John Y. Oliver; Ravishankar Rao; Paul Sultana; Jedidiah R. Crandall; Erik Czernikowski; Leslie W. Jones IV; Dean Copsey; Diana Keen; Venkatesh Akella; Frederic T. Chong (PACS, 2003)

High-performance optical-label switching packet routers and smart edge routers for the next-generation Internet. - S. J. Ben Yoo; Fei Xue; Yash Bansal; Julie Taylor; Zhong Pan; Jing Cao; Min-Yong Jeon; Tony Nady; Gary Goncher; Kirk Boyer; Kari Okamoto; Shin Kamei; et al. (IEEE J. Sel. Areas Commun., 2003)

Rate-distortion-complexity adaptive video compression and streaming. - Mihaela van der Schaar; Deepak S. Turaga; Venkatesh Akella (ICIP, 2004)

Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor. - John Y. Oliver; Ravishankar Rao; Paul Sultana; Jedidiah R. Crandall; Erik Czernikowski; Leslie W. Jones IV; Diana Franklin; Venkatesh Akella; Frederic T. Chong (ISCA, 2004)

Efficient orchestration of sub-word parallelism in media processors. - John Y. Oliver; Venkatesh Akella; Frederic T. Chong (SPAA, 2004)

Generic modeling of complexity for motion-compensated wavelet video decoders. - Gouri Landge; Mihaela van der Schaar; Venkatesh Akella (Electronic Imaging: Image and Video Communications and Processing, 2005)

Complexity metric driven energy optimization framework for implementing MPEG-21 scalable video decoders. - Gouri Landge; Mihaela van der Schaar; Venkatesh Akella (ICASSP (2), 2005)

Scheduling optical packets in wavelength, time, and space domains for all-optical packet switching routers. - Haijun Yang; Venkatesh Akella; Chen-Nee Chuah; S. J. Ben Yoo (ICC, 2005)

Proactive Energy Optimization Algorithms for Wavelet-Based Video Codecs on Power-Aware Processors. - Venkatesh Akella; Mihaela van der Schaar; Wen-Fu Kao (ICME, 2005)

Tile size selection for low-power tile-based architectures. - John Y. Oliver; Ravishankar Rao; Michael Brown; Jennifer Mankin; Diana Franklin; Frederic T. Chong; Venkatesh Akella (Conf. Computing Frontiers, 2006)

Segmented Bitline Cache: Exploiting Non-uniform Memory Access Patterns. - Ravishankar Rao; Justin Wenck; Diana Franklin; Rajeevan Amirtharajah; Venkatesh Akella (HiPC, 2006)

Synchroscalar: Evaluation of an embedded, multi-core architecture for media applications. - John Y. Oliver; Ravishankar Rao; Diana Franklin; Frederic T. Chong; Venkatesh Akella (J. Embed. Comput., 2006)

Life Cycle Aware Computing: Reusing Silicon Technology. - John Y. Oliver; Rajeevan Amirtharajah; Venkatesh Akella; Roland Geyer; Frederic T. Chong (Computer, 2007)

Using Application Bisection Bandwidth to Guide Tile Size Selection for the Synchroscalar Tile-Based Architecture. - John Y. Oliver; Diana Franklin; Frederic T. Chong; Venkatesh Akella (Trans. High Perform. Embed. Archit. Compil., 2007)

Credit-based dynamic reliability management using online wearout detection. - John Y. Oliver; Rajeevan Amirtharajah; Venkatesh Akella; Frederic T. Chong (Conf. Computing Frontiers, 2008)

OCDIMM: Scaling the DRAM Memory Wall Using WDM Based Optical Interconnects. - Amit Hadke; Tony Benavides; S. J. Ben Yoo; Rajeevan Amirtharajah; Venkatesh Akella (Hot Interconnects, 2008)

Design and evaluation of an optical CPU-DRAM interconnect. - Amit Hadke; Tony Benavides; Rajeevan Amirtharajah; Matthew K. Farrens; Venkatesh Akella (ICCD, 2008)

FPGA-based low-complexity high-throughput tri-mode decoder for quasi-cyclic LDPC codes. - Xiaoheng Chen; Qin Huang 002; Shu Lin 001; Venkatesh Akella (Allerton, 2009)

Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing. - Xiaoheng Chen; Jingyu Kang; Shu Lin 001; Venkatesh Akella (DATE, 2009)

Markov decision process (MDP) framework for optimizing software on mobile phones. - Tang Lung Cheung; Kari Okamoto; Frank Maker III; Xin Liu 002; Venkatesh Akella (EMSOFT, 2009)

DOS: a scalable optical switch for datacenters. - Xiaohui Ye; Yawei Yin; S. J. Ben Yoo; Paul Vincent Mejia; Roberto Proietti; Venkatesh Akella (ANCS, 2010)

Performance Evaluation of a Multicore System with Optically Connected Memory Modules. - Paul Vincent Mejia; Rajeevan Amirtharajah; Matthew K. Farrens; Venkatesh Akella (NOCS, 2010)

Markov decision process (MDP) framework for software power optimization using call profiles on mobile phones. - Eric Jung; Frank Maker III; Tang Lung Cheung; Xin Liu 002; Venkatesh Akella (Des. Autom. Embed. Syst., 2010)

Optical Router Control Architecture and Contention Resolution Algorithms Capable of Asynchronous, Variable-Length Packet Switching. - Haijun Yang; Zhong Pan; Venkatesh Akella; Chen-Nee Chuah; S. J. Ben Yoo (JOCN, 2010)

QSN - A Simple Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders. - Xiaoheng Chen; Shu Lin 001; Venkatesh Akella (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Addressing system-level trimming issues in on-chip nanophotonic networks. - Christopher Nitta; Matthew K. Farrens; Venkatesh Akella (HPCA, 2011)

Resilient microring resonator based photonic networks. - Christopher Nitta; Matthew K. Farrens; Venkatesh Akella (MICRO, 2011)

Inferring packet dependencies to improve trace based simulation of on-chip networks. - Christopher Nitta; Kevin Macdonald; Matthew K. Farrens; Venkatesh Akella (NOCS, 2011)

Buffering and Flow Control in Optical Switches for High Performance Computing. - Xiaohui Ye; Roberto Proietti; Yawei Yin; S. J. Ben Yoo; Venkatesh Akella (JOCN, 2011)

Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders. - Xiaoheng Chen; Jingyu Kang; Shu Lin 001; Venkatesh Akella (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Hardware Implementation of a Backtracking-Based Reconfigurable Decoder for Lowering the Error Floor of Quasi-Cyclic LDPC Codes. - Xiaoheng Chen; Jingyu Kang; Shu Lin 001; Venkatesh Akella (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Exploiting data-level parallelism for energy-efficient implementation of LDPC decoders and DCT on an FPGA. - Xiaoheng Chen; Venkatesh Akella (ACM Trans. Reconfigurable Technol. Syst., 2011)

DCAF - A Directly Connected Arbitration-Free Photonic Crossbar for Energy-Efficient High Performance Computing. - Christopher Nitta; Matthew K. Farrens; Venkatesh Akella (IPDPS, 2012)

DCOF - An Arbitration Free Directly Connected Optical Fabric. - Christopher Nitta; Matthew K. Farrens; Venkatesh Akella (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

AWGR-Based Optical Topologies for Scalable and Efficient Global Communications in Large-Scale Multi-Processor Systems. - Xiaohui Ye; S. J. Ben Yoo; Venkatesh Akella (JOCN, 2012)

Efficient Configurable Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes. - Xiaoheng Chen; Shu Lin 001; Venkatesh Akella (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Update rate tradeoffs for improving online power modeling in smartphones. - Frank Maker III; Rajeevan Amirtharajah; Venkatesh Akella (ISLPED, 2013)

Scalability and performance of a distributed AWGR-based all-optical token interconnect architecture. - Roberto Proietti; Christopher J. Nitta; Yawei Yin; Venkatesh Akella; S. J. Ben Yoo (OFC/NFOEC, 2013)

MELOADES: Methodology for long-term online adaptation of embedded software for heterogeneous devices. - Frank Maker III; Rajeevan Amirtharajah; Venkatesh Akella (J. Syst. Archit., 2013)

Runtime Adaptation of Applications Using Design Of Experiments: A Smartphone-Based Case Study. - Frank Maker III; Rajeevan Amirtharajah; Venkatesh Akella (IEEE Embed. Syst. Lett., 2014)

PDG_GEN: A Methodology for Fast and Accurate Simulation of On-Chip Networks. - Kevin Macdonald; Christopher Nitta; Matthew K. Farrens; Venkatesh Akella (IEEE Trans. Computers, 2014)

Simultaneously Reducing Latency and Power Consumption in OpenFlow Switches. - Paul Congdon; Prasant Mohapatra; Matthew K. Farrens; Venkatesh Akella (IEEE/ACM Trans. Netw., 2014)

Design space exploration of FPGA-based Deep Convolutional Neural Networks. - Mohammad Motamedi; Philipp Gysel; Venkatesh Akella; Soheil Ghiasi (ASP-DAC, 2016)

HogWild++: A New Mechanism for Decentralized Asynchronous Stochastic Gradient Descent. - Huan Zhang 001; Cho-Jui Hsieh; Venkatesh Akella (ICDM, 2016)

Photonic Interconnects for Interposer-based 2.5D/3D Integrated Systems on a Chip. - Paolo Grani; Roberto Proietti; Venkatesh Akella; S. J. Ben Yoo (MEMSYS, 2016)

Design and Evaluation of AWGR-Based Photonic NoC Architectures for 2.5D Integrated High Performance Computing Systems. - Paolo Grani; Roberto Proietti; Venkatesh Akella; S. J. Ben Yoo (HPCA, 2017)

Improving Execution Time of Parallel Programs on Large Scale Chip Multiprocessors with Constant Average Power Processing. - Kramer Straube; Christopher Nitta; Raj Amirtharajah; Matthew K. Farrens; Venkatesh Akella (ICCD, 2017)

Scalable Hardware Accelerator for Mini-Batch Gradient Descent. - Sandeep Rasoori; Venkatesh Akella (ACM Great Lakes Symposium on VLSI, 2018)

Improving Provisioned Power Efficiency in HPC Systems with GPU-CAPP. - Kramer Straube; Jason Lowe-Power; Christopher Nitta; Matthew K. Farrens; Venkatesh Akella (HiPC, 2018)

A case for exposing extra-architectural state in the ISA: position paper. - Jason Lowe-Power; Venkatesh Akella; Matthew K. Farrens; Samuel T. King; Christopher J. Nitta (HASP@ISCA, 2018)

Multiplier-Free Implementation of Galois Field Fourier Transform on a FPGA. - Sree Balaji Girisankar; Mona Nasseri; Jennifer Priscilla; Shu Lin 001; Venkatesh Akella (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

AutoTM: Automatic Tensor Movement in Heterogeneous Memory Systems using Integer Linear Programming. - Mark Hildebrand; Jawad Khan; Sanjeev Trika; Jason Lowe-Power; Venkatesh Akella (ASPLOS, 2020)

HCAPP: Scalable Power Control for Heterogeneous 2.5D Integrated Systems. - Kramer Straube; Jason Lowe-Power; Christopher Nitta; Matthew K. Farrens; Venkatesh Akella (ICPP, 2020)

Predicting soil permanganate oxidizable carbon (POXC) by coupling DRIFT spectroscopy and artificial neural networks (ANN). - Andrew Margenot; Terry O'Neill; Rolf Sommer; Venkatesh Akella (Comput. Electron. Agric., 2020)

Performance Analysis of Scientific Computing Workloads on Trusted Execution Environments. - Ayaz Akram; Anna Giannakou; Venkatesh Akella; Jason Lowe-Power; Sean Peisert (CoRR, 2020)

FPGA and GPU-based acceleration of ML workloads on Amazon cloud - A case study using gradient boosted decision tree library. - Maxim Shepovalov; Venkatesh Akella (Integr., 2020)

Performance Analysis of Scientific Computing Workloads on General Purpose TEEs. - Ayaz Akram; Anna Giannakou; Venkatesh Akella; Jason Lowe-Power; Sean Peisert (IPDPS, 2021)

A Case Against Hardware Managed DRAM Caches for NVRAM Based Systems. - Mark Hildebrand; Julian T. Angeles; Jason Lowe-Power; Venkatesh Akella (ISPASS, 2021)

HTA: A Scalable High-Throughput Accelerator for Irregular HPC Workloads. - Pouya Fotouhi; Marjan Fariborz; Roberto Proietti; Jason Lowe-Power; Venkatesh Akella; S. J. Ben Yoo (ISC, 2021)

SoK: Limitations of Confidential Computing via TEEs for High-Performance Compute Systems. - Ayaz Akram; Venkatesh Akella; Sean Peisert; Jason Lowe-Power (SEED, 2022)

LLM: Realizing Low-Latency Memory by Exploiting Embedded Silicon Photonics for Irregular Workloads. - Marjan Fariborz; Mahyar Samani; Pouya Fotouhi; Roberto Proietti; Il-Min Yi; Venkatesh Akella; Jason Lowe-Power; Samuel Palermo; S. J. Ben Yoo (ISC, 2022)

A Model for Scalable and Balanced Accelerators for Graph Processing. - Marjan Fariborz; Mahyar Samani; Terry O'Neill; Jason Lowe-Power; S. J. Ben Yoo; Venkatesh Akella (IEEE Comput. Archit. Lett., 2022)

Scalable Hardware Acceleration of Graph Processing with Photonic Interconnects. - Venkatesh Akella; Marjan Fariborz; Mahyar Samani; S. J. Ben Yoo; Jason Lowe-Power (PSC, 2023)

Efficient Large Scale DLRM Implementation on Heterogeneous Memory Systems. - Mark Hildebrand; Jason Lowe-Power; Venkatesh Akella (ISC, 2023)

CachedArrays: Optimizing Data Movement for Heterogeneous Memory Systems. - Mark Hildebrand; Jason Lowe-Power; Venkatesh Akella (IPDPS, 2024)

TEGRA - Scaling Up Terascale Graph Processing with Disaggregated Computing. - William Shaddix; Mahyar Samani; Marjan Fariborz; S. J. Ben Yoo; Jason Lowe-Power; Venkatesh Akella (CoRR, 2024)

NOVA: A Novel Vertex Management Architecture for Scalable Graph Processing. - Marjan Fariborz; Mahyar Samani; Austin York; S. J. Ben Yoo; Jason Lowe-Power; Venkatesh Akella (HPCA, 2025)