graze: A Tool for Performance Visualization and Analysis. - Lantz Moore; Debra A. Hensgen; David Charley; Venkatram Krishnaswamy; Dale E. Martin; Timothy J. McBrayer; Philip A. Wilsey (ICPP (2), 1995)

System Modeling, Performance Analysis, and Evolutionary Prototyping with Hardware Description Languages. - Sidharta Mohanty; Venkatram Krishnaswamy; Philip A. Wilsey (MASCOTS, 1995)

Actor Based Parallel VHDL Simulation Using Time Warp. - Venkatram Krishnaswamy; Prithviraj Banerjee (Workshop on Parallel and Distributed Simulation, 1996)

A procedure for software synthesis from VHDL models. - Venkatram Krishnaswamy; Rajesh Gupta 001; Prithviraj Banerjee (ASP-DAC, 1997)

Load Balancing and Workload Minimization Of Overlapping Parallel Tasks. - Venkatram Krishnaswamy; Gagan Hasteer; Prithviraj Banerjee (ICPP, 1997)

Performance Evaluation of Message-Driven Parallel VLSI CAD Applications on General Purpose Multiprocessors. - John G. Holm; John A. Chandy; Steven Parkes; Sumit Roy 003; Venkatram Krishnaswamy; Gagan Hasteer; Prithviraj Banerjee (International Conference on Supercomputing, 1997)

Implications of VHDL timing models on simulation and software synthesis. - Venkatram Krishnaswamy; Rajesh Gupta 001; Prithviraj Banerjee (J. Syst. Archit., 1997)

Parallel Algorithms for VHDL Simulation - Venkatram Krishnaswamy (1997)

WADE: a Web-based automated parallel CAD environment. - Dhruva R. Chakrabarti; Pramod G. Joisha; John A. Chandy; Krishnaswamy Krishnaswamy; Venkatram Krishnaswamy; Prithviraj Banerjee (HiPC, 1998)

Parallel Compiled Event Driven VHDL Simulation. - Venkatram Krishnaswamy; Prithviraj Banerjee (International Conference on Supercomputing, 1998)

A switch level fault simulation environment. - Venkatram Krishnaswamy; Jeremy Casas; Thomas Tetzlaff (DAC, 2000)

A study of bridging defect probabilities on a Pentium (TM) 4 CPU. - Venkatram Krishnaswamy; A. B. Ma; Praveen Vishakantaiah (ITC, 2001)

Automatic Parallelization of Compiled Event Driven VHDL Simulation. - Venkatram Krishnaswamy; Gagan Hasteer; Prithviraj Banerjee (IEEE Trans. Computers, 2002)

Bandwidth and power management of glueless 8-socket SPARC T5 system. - Venkatram Krishnaswamy; Dawei Huang; Sebastian Turullols; Jinuk Luke Shin (ISSCC, 2013)

Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a 28nm SPARC M6 processor. - Yifan YangGong; Sebastian Turullols; Daniel Woo; Changku Huang; King C. Yen; Venkatram Krishnaswamy; Kalon Holdbrook; Jinuk Luke Shin (A-SSCC, 2014)

A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm. - Jason Hart; Hoyeol Cho; Yuefei Ge; Gregory Gruber; Dawei Huang; Changku Hwang; Daisy Jian; Timothy Johnson; Georgios K. Konstadinidis; Venkatram Krishnaswamy; Lance Kwong; Robert P. Masleid; et al. (IEEE J. Solid State Circuits, 2014)

4.3 Fine-grained adaptive power management of the SPARC M7 processor. - Venkatram Krishnaswamy; Jeffrey Brooks; Georgios K. Konstadinidis; Curtis McAllister; Ha Pham; Sebastian Turullols; Jinuk Luke Shin; Yifan YangGong; Haowei Zhang (ISSCC, 2015)

4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor. - Penny Li; Jinuk Luke Shin; Georgios K. Konstadinidis; Francis Schumacher; Venkatram Krishnaswamy; Hoyeol Cho; Sudesna Dash; Robert P. Masleid; Chaoyang Zheng; Yuanjung David Lin; Paul Loewenstein; Heechoul Park; et al. (ISSCC, 2015)

SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor. - Georgios K. Konstadinidis; Hongping Penny Li; Francis Schumacher; Venkatram Krishnaswamy; Hoyeol Cho; Sudesna Dash; Robert P. Masleid; Chaoyang Zheng; Yuanjung David Lin; Paul Loewenstein; Heechoul Park; Vijay Srinivasan; et al. (IEEE J. Solid State Circuits, 2016)