Processor subsystem interconnect architecture for a large symmetric multiprocessing system. - Pak-kin Mak; Gary E. Strait; Michael A. Blake; Kevin W. Kark; Vesselina K. Papazova; A. E. (Rick) Seigler; Gary A. Van Huben; Liyong Wang; George C. Wellwood (IBM J. Res. Dev., 2004)

IBM zEnterprise redundant array of independent memory subsystem. - Patrick J. Meaney; Luis Alfonso Lastras-Montaño; Vesselina K. Papazova; Eldee Stephens; J. S. Johnson; Luiz C. Alves; James A. O'Connor; William J. Clarke (IBM J. Res. Dev., 2012)

The IBM z13 processor cache subsystem. - Craig R. Walters; Pak-kin Mak; Deanna Postles Dunn Berger; Michael A. Blake; Tim Bronson; K. D. Klapproth; A. J. O'Neill; Robert J. Sonnelitter; Vesselina K. Papazova (IBM J. Res. Dev., 2015)

Design of the IBM z14 microprocessor. - Christian Jacobi 002; Anthony Saporito; Martin Recktenwald; Aaron Tsai; Ulrich Mayer; Markus M. Helms; Adam Collura; Pak-kin Mak; Robert J. Sonnelitter; Michael A. Blake; Tim Bronson; Arthur O'neill; et al. (IBM J. Res. Dev., 2018)

Design of the IBM z15 microprocessor. - Anthony Saporito; Martin Recktenwald; Christian Jacobi 002; Gerrit Koch; Deanna Postles Dunn Berger; Robert J. Sonnelitter; Craig R. Walters; Jang-Soo Lee; Cédric Lichtenau; Ulrich Mayer; Eduard Herkel; Stefan Payer; et al. (IBM J. Res. Dev., 2020)