ARI: Adaptive LLC-memory traffic management. - Viacheslav V. Fedorov; Sheng Qiu; A. L. Narasimha Reddy; Paul V. Gratz (ACM Trans. Archit. Code Optim., 2013)

An area-efficient Ternary CAM design using floating gate transistors. - Viacheslav V. Fedorov; Monther Abusultan; Sunil P. Khatri (ICCD, 2014)

Shared Last-Level Caches and The Case for Longer Timeslices. - Viacheslav V. Fedorov; A. L. Narasimha Reddy; Paul V. Gratz (MEMSYS, 2015)

Dynamic Memory Pressure Aware Ballooning. - Jinchun Kim; Viacheslav V. Fedorov; Paul V. Gratz; A. L. Narasimha Reddy (MEMSYS, 2015)

FTCAM: An Area-Efficient Flash-Based Ternary CAM Design. - Viacheslav V. Fedorov; Monther Abusultan; Sunil P. Khatri (IEEE Trans. Computers, 2016)

Speculative paging for future NVM storage. - Viacheslav V. Fedorov; Jinchun Kim; Mian Qin; Paul V. Gratz; A. L. Narasimha Reddy (MEMSYS, 2017)

Hardware Acceleration of Hash Operations in Modern Microprocessors. - Abbas A. Fairouz; Monther Abusultan; Viacheslav V. Fedorov; Sunil P. Khatri (IEEE Trans. Computers, 2021)