Efficient FPGA-based QPSK Demodulation Loops: Application to the DVB Standard. - Francisco Cardells-Tormo; Javier Valls-Coquillat; Vicenc Almenar-Terre; Vicente Torres-Carot (FPL, 2002)

DIGIMOD: A Tool to Implement FPGA-Based Digital IF and Baseband Modems. - José Marín-Roig; Vicente Torres-Carot; Ma José Canet; Asuncion Perez-Pascual; Trinidad Sansaloni; Francisco Cardells-Tormo; Fabian Angarita; Felip Vicedo; Vicenc Almenar-Terre; Javier Valls-Coquillat (FPL, 2003)

Design of high performance timing recovery loops for communication applications. - Vicente Torres-Carot; A. Perez-Pascual; T. Sansaloni; Javier Valls (SiPS, 2006)

The use of CORDIC in software defined radios: a tutorial. - Javier Valls; Trinidad Sansaloni; Asuncion Perez-Pascual; Vicente Torres 001; Vicenç Almenar (IEEE Commun. Mag., 2006)

Design of an efficient digital down-converter for a SDR-based DVB-S receiver. - A. Perez-Pascual; T. Sansaloni; Vicente Torres 001; Vicenç Almenar; Javier Valls (ECCTD, 2007)

FFT Spectrum Analyzer Project for Teaching Digital Signal Processing With FPGA Devices. - Trinidad Sansaloni; Asuncion Perez-Pascual; Vicente Torres-Carot; Vicenç Almenar; José F. Toledo; Javier Valls (IEEE Trans. Educ., 2007)

Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs. - T. Sansaloni; A. Perez-Pascual; Vicente Torres-Carot; Javier Valls (J. VLSI Signal Process., 2007)

Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems. - A. Perez-Pascual; T. Sansaloni; Vicente Torres-Carot; Vicenc Almenar-Terre; Javier Valls (J. Signal Process. Syst., 2009)

Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications. - Vicente Torres-Carot; A. Perez-Pascual; T. Sansaloni; Javier Valls (J. Signal Process. Syst., 2009)

FPGA-implementation of atan(Y/X) based on logarithmic transformation and LUT-based techniques. - Roberto Gutiérrez; Vicente Torres-Carot; Javier Valls-Coquillat (J. Syst. Archit., 2010)

High-throughput FPGA-based emulator for structured LDPC codes. - Fabian Angarita; Vicente Torres-Carot; Asuncion Perez-Pascual; Javier Valls (ICECS, 2012)

Fully-parallel LUT-based (2048, 1723) LDPC code decoder for FPGA. - Vicente Torres-Carot; Asuncion Perez-Pascual; Trinidad Sansaloni; Javier Valls (ICECS, 2012)

Hardware Architecture of a Gaussian Noise Generator Based on the Inversion Method. - Roberto Gutiérrez; Vicente Torres-Carot; Javier Valls (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Reduced-Complexity Min-Sum Algorithm for Decoding LDPC Codes With Low Error-Floor. - Fabian Angarita; Javier Valls; Vicenç Almenar; Vicente Torres-Carot (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Fast- and Low-Complexity atan2(a, b) Approximation [Tips and Tricks]. - Vicente Torres 001; Javier Valls; Richard G. Lyons (IEEE Signal Process. Mag., 2017)

A Fast and Low-Complexity Operator for the Computation of the Arctangent of a Complex Number. - Vicente Torres 001; Javier Valls (IEEE Trans. Very Large Scale Integr. Syst., 2017)

High-Throughput One-Channel RS(255, 239) Decoder. - Gabriele Perrone; Javier Valls; Vicente Torres 001; Francisco Miguel Garcia-Herrero (DSD, 2018)

Soft-decision LCC Decoder Architecture with n=4 for RS(255, 239). - Vicente Torres 001; Javier Valls; María José Canet; Francisco Garcia-Herrero (NEWCAS, 2018)

Reed-Solomon Decoder Based on a Modified ePIBMA for Low-Latency 100 Gbps Communication Systems. - Gabriele Perrone; Javier Valls; Vicente Torres 001; Francisco Garcia-Herrero (Circuits Syst. Signal Process., 2019)

A Test Vector Generation Method Based on Symbol Error Probabilities for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding. - Javier Valls; Vicente Torres 001; María José Canet; Francisco Miguel Garcia-Herrero (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)