System-Level Behavioral Model of a 12-Bit 1.5-Bit Per Stage Pipelined ADC Based on Verilog®=-AMS. - Vicente Yair Ponce-Hinestroza; Victor R. Gonzalez-Diaz (SMACD, 2018)

Simulation Platform for a VANET Using the TrueTime Toolbox: Further Result Toward Cyber-Physical Vehicle Systems. - Alejandro Garcia-Santiago; Josefina Castañeda-Camacho; José-Fermi Guerrero-Castellanos; Gerardo Mino Aguilar; Vicente Yair Ponce-Hinestroza (VTC Fall, 2018)

Pipeline A/D Converter Design for 5G OFDM Communications Systems. - Vicente Yair Ponce-Hinestroza; Josefina Castañeda-Camacho; Victor R. Gonzalez-Diaz; Gerardo Mino Aguilar; Alejandro Garcia-Santiago (VTC Fall, 2018)