A repeater timing model and insertion algorithm to reduce delay in RC tree structures. - Victor Adler; Eby G. Friedman (ICECS, 1998)

Exploiting hysteresis in a CMOS buffer. - Radu M. Secareanu; Victor Adler; Eby G. Friedman (ICECS, 1999)

Demonstration of speed enhancements on an industrial circuit through application of non-zero clock skew scheduling. - Dimitrios Velenis; Kevin T. Tang; Ivan S. Kourtev; Victor Adler; Franklin Baez; Eby G. Friedman (ICECS, 2001)

The first MAJC microprocessor: a dual CPU system-on-a-chip. - Andre Kowalczyk; Victor Adler; Chaim Amir; Frank Chiu; Choon Ping Chng; Willem J. de Lange; Yuefei Ge; Subhendra Ghosh; Tan Canh Hoang; Baoqing Huang; Shree Kant; Y. S. Kao; et al. (IEEE J. Solid State Circuits, 2001)

Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling. - Dimitrios Velenis; Kevin T. Tang; Ivan S. Kourtev; Victor Adler; Franklin Baez; Eby G. Friedman (J. Circuits Syst. Comput., 2002)