Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM. - Jun-Fu Huang; Victor C. Y. Chang; Sally Liu; Kelvin Y. Y. Doong; Keh-Jeng Chang (ASP-DAC, 2007)

Power saving and noise reduction of 28nm CMOS RF system integration using integrated fan-out wafer level packaging (InFO-WLP) technology. - Chuei-Tang Wang; Jeng-Shien Hsieh; Victor C. Y. Chang; En-Hsiang Yeh; Feng-Wei Kuo; Hsu-Hsien Chen; Chih-Hua Chen; Huan-Neng Ron Chen; Ying-Ta Lu; Chewnpu Jou; Hao-Yi Tsai; C. S. Liu; et al. (3DIC, 2015)

Accurate 3-D capacitance extractions for advanced nanometer CMOS nodes. - Keh-Jeng Chang; Shih-Hao Lee; Kuo-Fu Lee; Ping-Hung Yuh; Ho-Che Yu; Wen-Cheng Huang; Victor C. Y. Chang (VLSI-DAT, 2015)

Systolic Building Block for Logic-on-Logic 3D-IC Implementations of Convolutional Neural Networks. - H. T. Kung 001; Bradley McDanel; Sai Qian Zhang; C. T. Wang; Jin Cai; C. Y. Chen; Victor C. Y. Chang; M. F. Chen; Jack Yuan-Chen Sun; Douglas Yu (ISCAS, 2019)