Partial Scan High-Level Synthesis. - Víctor Fernández 001; Pablo Sánchez (ED&TC, 1996)

Single Source Design Environment for Embedded Systems Based on SystemC. - Hector Posadas; Fernando Herrera; Víctor Fernández 001; Pablo Sánchez; Eugenio Villar; Francisco Blasco (Des. Autom. Embed. Syst., 2004)

Hardware Aware eIRA LDPC Code Generation. - J. M. Perez; Víctor Fernández 001 (ISWCS, 2005)

Optimizing Data-Flow Graphs with min/max, adding and relational operations. - Jesús M. Pérez; Pablo Sánchez; Víctor Fernández 001 (DATE, 2010)

Formal Support for Untimed SystemC Specifications: Application to High-level Synthesis. - Eugenio Villar; Fernando Herrera; Víctor Fernández 001 (FDL, 2010)

SystemC-MDVP modelling of pressure driven microfluidic systems. - Víctor Fernández 001; Elier Wilpert; Herique Isidoro; Cédric Ben Aoun; François Pêcheux (MECO, 2014)

Virtual prototyping of pressure driven microfluidic systems with SystemC-AMS extensions. - Víctor Fernández 001; Andrés Mena; Cédric Ben Aoun; François Pêcheux; Luis J. Fernández (Microprocess. Microsystems, 2015)

Design Space Exploration in Heterogeneous Platforms Using OpenMP. - Ángel Álvarez; Íñigo Ugarte; Víctor Fernández 001; Pablo Sánchez (DCIS, 2019)

OpenMP Dynamic Device Offloading in Heterogeneous Platforms. - Ángel Álvarez; Íñigo Ugarte; Víctor Fernández 001; Pablo Sánchez (IWOMP, 2019)

Pre-Silicon FEC Decoding Verification on SoC FPGAs. - Víctor Fernández 001; Carlos Abad; Ángel Álvarez; Íñigo Ugarte; Pablo Sánchez (IEEE Commun. Lett., 2021)

An Efficient NB-LDPC Decoder Architecture for Space Telecommand Links. - Ángel Álvarez; Víctor Fernández 001; Balázs Matuz (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

UML-Based Design Flow for Systems with Neural Networks. - Daniel Suárez; Héctor Posadas; Víctor Fernández 001 (DCIS, 2023)

Accelerating the Verification of Forward Error Correction Decoders by PCIe FPGA Cards. - Daniel Suárez; Víctor Fernández 001; Héctor Posadas; Pablo Sánchez (IEEE Embed. Syst. Lett., 2023)

CNN-LSTM Implementation Methodology on SoC FPGA for Human Action Recognition Based on Video. - Daniel Suárez; Víctor Fernández 001; Héctor Posadas (DSD, 2024)