A 64-MHz clock-rate ΣΔ ADC with 88-dB SNDR and -105-dB IM3 distortion at a 1.5-MHz signal frequency. - Sandeep K. Gupta 003; Victor Fong (IEEE J. Solid State Circuits, 2002)

A 5-GHz direct-conversion CMOS transceiver utilizing automatic frequency control for the IEEE 802.11a wireless LAN standard. - Arya Behzad; Zhong Ming Shi; Seema Butala Anand; Li Lin; Keith A. Carter; Michael S. Kappes; Tsung-Hsien Lin; Thinh Nguyen; Dan Yuan; Stephen Wu 003; Y. C. Wong; Victor Fong; et al. (IEEE J. Solid State Circuits, 2003)

An 11.5-ENOB 100-MS/s 8mW dual-reference SAR ADC in 28nm CMOS. - Michael A. Inerfield; Abhishek Kamath; Feng Su; Jason Hu; Xinyu Yu; Victor Fong; Omar Alnaggar; Fang Lin; Tom Kwan (VLSIC, 2014)