Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS. - Rosa Rodríguez-Montañés; Jaume A. Segura 001; Víctor H. Champac; Joan Figueras; J. A. Rubio (ITC, 1991)

Quiescent current analysis and experimentation of defective CMOS circuits. - Jaume A. Segura 001; Víctor H. Champac; Rosa Rodríguez-Montañés; Joan Figueras; J. A. Rubio (J. Electron. Test., 1992)

Analysis of the Floating Gate Defect in CMOS. - Víctor H. Champac; Antonio Rubio 001; Joan Figueras (DFT, 1993)

Electrical model of the floating gate defect in CMOS ICs: implications on IDDQ testing. - Víctor H. Champac; Antonio Rubio 001; Joan Figueras (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Testability of floating gate defects in sequential circuits. - Víctor H. Champac; Joan Figueras (VTS, 1995)

Current Testing of CMOS Combinational Circuits with Single Floating Gate Defects. - Víctor H. Champac; Joan Figueras (VLSI Design, 1997)

A Graph-Oriented CAD Tool for Establishing the Topological Diagnostic Conditions of Analogue Circuits. - Arturo Sarmiento-Reyes; Miguel Ángel Gutiérrez de Anda; Víctor H. Champac (SBCCI, 1998)

IDDQ Testing of Opens in CMOS SRAMs. - Víctor H. Champac; José Castillejos; Joan Figueras (J. Electron. Test., 1999)

Detectability Dependency on Test Generation Process for Interconnection Opens. - Antonio Zenteno; Víctor H. Champac; Joan Figueras (LATW, 2000)

Detectability Conditions for Interconnection Open Defect. - Víctor H. Champac; Antonio Zenteno (VTS, 2000)

CGTDEMO - educational software for the central limit theorem. - Gordana Jovanovic-Dolecek; Víctor H. Champac (ACM SIGCSE Bull., 2000)

Test of Data Retention Faults Sensing the Bit Line with a DFT Bases Differential Amplifier. - Víctor H. Champac; Victor Avendaño; Gordana Jovanovic-Dolecek (LATW, 2001)

Dynamic Signal X-Y Zoning and its Applicability to Detect Time Critical Defects in the Digital Domain. - Anotnio Zenteno; Víctor H. Champac; Joan Figueras (LATW, 2001)

Resistive Opens in a Class of CMOS Latches: Analysis and DFT. - Antonio Zenteno; Víctor H. Champac (VTS, 2001)

Guest Editorial. - Marcelo Lubaszewski; Víctor H. Champac (J. Electron. Test., 2001)

Detectability Conditions of Full Opens in the Interconnections. - Antonio Zenteno; Víctor H. Champac; Joan Figueras (J. Electron. Test., 2001)

A new technique for noise-tolerant pipelined dynamic digital circuits. - Fernando Mendoza-Hernandez; Mónico Linares Aranda; Víctor H. Champac; Alejandro Díaz-Sánchez (ISCAS (4), 2002)

Behavior Analysis and Testing of Resistive Opens in the Clock Circuitry of Memory Elements. - Antonio Zenteno; Víctor H. Champac; Jaime Ramírez-Angulo (LATW, 2002)

Signal integrity loss in bus lines due to open shielding defects. - Victor Avendaño; Víctor H. Champac; Joan Figueras (ETW, 2003)

Guest Editorial. - Víctor H. Champac; Ingrid Jansch-Pôrto (J. Electron. Test., 2003)

Analysis and Attenuation Proposal in Ground Bounce. - Antonio Zenteno; Víctor H. Champac; Michel Renovell; Florence Azaïs (Asian Test Symposium, 2004)

Signal integrity verification using high speed monitors. - Victor Avendaño; Víctor H. Champac; Joan Figueras (ETS, 2004)

An improved technique to increase noise-tolerance in dynamic digital circuits. - Fernando Mendoza-Hernandez; Mónico Linares Aranda; Víctor H. Champac Vilela (ISCAS (2), 2004)

The noise immunity of dynamic digital circuits with technology scaling. - Fernando Mendoza-Hernandez; Mónico Linares Aranda; Víctor H. Champac Vilela (ISCAS (2), 2004)

Guest Editorial. - Fabian Vargas 001; Víctor H. Champac (J. Electron. Test., 2004)

Test of Interconnection Opens Considering Coupling Signals. - Roberto Gómez 001; Alejandro Girón; Víctor H. Champac (DFT, 2005)

Testing of resistive opens in CMOS latches and flip-flops. - Víctor H. Champac; Antonio Zenteno; José L. Garcia (ETS, 2005)

Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops. - Antonio Zenteno Ramírez; Guillermo Espinosa; Víctor H. Champac (IEEE Trans. Very Large Scale Integr. Syst., 2007)

A design methodology for logic paths tolerant to local intra-die variations. - Daniel Iparraguirre-Cardenas; Jose Luis Garcia-Gervacio; Víctor H. Champac (ISCAS, 2008)

Testing Skew and Logic Faults in SoC Interconnects. - Nestor Hernandez; Víctor H. Champac (ISVLSI, 2008)

A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines. - Roberto Gómez 001; Alejandro Girón; Víctor H. Champac (J. Electron. Test., 2008)

Detectability analysis of small delays due to resistive opens considering process variations. - Jose Luis Garcia-Gervacio; Víctor H. Champac (IOLTS, 2009)

Built-in aging monitoring for safety-critical applications. - Julio César Vázquez; Víctor H. Champac; Adriel Ziesemer; Ricardo Reis 001; Isabel C. Teixeira; Marcelino B. Santos; João Paulo Teixeira 001 (IOLTS, 2009)

A modern look at the CMOS stuck-open fault. - Roberto Gómez 001; Víctor H. Champac; Chuck Hawkins; Jaume Segura 001 (LATW, 2009)

Stuck-Open Fault Leakage and Testing in Nanometer Technologies. - Julio César Vázquez; Víctor H. Champac; Chuck Hawkins; Jaume Segura 001 (VTS, 2009)

Programmable aging sensor for automotive safety-critical applications. - Julio César Vázquez; Víctor H. Champac; Isabel C. Teixeira; Marcelino B. Santos; João Paulo Teixeira 001 (DATE, 2010)

Computing the detection of Small Delay Defects caused by resistive opens of nanometer ICs. - Jose Luis Garcia-Gervacio; Víctor H. Champac (ETS, 2010)

Predictive error detection by on-line aging monitoring. - Julio César Vázquez; Víctor H. Champac; Adriel Ziesemer; Ricardo Reis 001; Jorge Semião; Isabel C. Teixeira; Marcelino B. Santos; João Paulo Teixeira 001 (IOLTS, 2010)

Reliability analysis of small delay defects in vias located in signal paths. - Hector Villacorta; Víctor H. Champac; Chuck Hawkins; Jaume Segura 001 (LATW, 2010)

Low-sensitivity to process variations aging sensor for automotive safety-critical applications. - Julio César Vázquez; Víctor H. Champac; Adriel Ziesemer; Ricardo Reis 001; Isabel Maria Cacho Teixeira; Marcelino B. Santos; João Paulo Teixeira 001 (VTS, 2010)

Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals. - Víctor H. Champac; Victor Avendaño; Joan Figueras (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors. - Celestino V. Martins; Jorge Semião; Julio César Vázquez; Víctor H. Champac; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (VTS, 2011)

A new methodology for realistic open defect detection probability evaluation under process variations. - Jesús Moreno; Víctor H. Champac; Michel Renovell (VTS, 2011)

Computing the Detection Probability for Small Delay Defects of Nanometer ICs. - Jose Luis Garcia-Gervacio; Víctor H. Champac (J. Electron. Test., 2011)

12th "IEEE Latin-American Test Workshop" Porto de Galinhas, Brazil, 27-30 March 2011. - Víctor H. Champac; Fernanda Gusmão de Lima Kastensmidt; Letícia Maria Veiras Bolzani Poehls; Fabian Vargas 001; Yervant Zorian (J. Low Power Electron., 2011)

Low voltage testing for interconnect opens under process variations. - Jesús Moreno; Víctor H. Champac; Michel Renovell (LATW, 2012)

Small-delay defects detection under process variation using Inter-Path Correlation. - Francisco J. Galarza-Medina; Jose Luis Garcia-Gervacio; Víctor H. Champac; Alex Orailoglu (VTS, 2012)

Testing of Stuck-Open Faults in Nanometer Technologies. - Víctor H. Champac; Julio Vazquez Hernandez; Salvador Barceló; Roberto Gómez 001; Chuck Hawkins; Jaume Segura 001 (IEEE Des. Test Comput., 2012)

Aging-Aware Power or Frequency Tuning With Predictive Fault Detection. - Jackson Pachito; Celestino V. Martins; Bruno Jacinto; Jorge Semião; Julio César Vázquez; Víctor H. Champac; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (IEEE Des. Test Comput., 2012)

Resistive bridge defect detection enhancement under parameter variations combining Low VDD and body bias in a delay based test. - Hector Villacorta; Víctor H. Champac; Sebastià A. Bota; Jaume Segura 001 (Microelectron. Reliab., 2012)

Bridge defect detection in nanometer CMOS circuits using Low VDD and body bias. - Hector Villacorta; Jose Luis Garcia-Gervacio; Víctor H. Champac; Sebastià A. Bota; Jaime Martínez-Castillo; Jaume Segura 001 (LATW, 2013)

Reliability Analysis of Small-Delay Defects Due to Via Narrowing in Signal Paths. - Hector Villacorta; Charles F. Hawkins; Víctor H. Champac; Jaume Segura 001; Roberto Gómez 001 (IEEE Des. Test, 2013)

Process Variations-Aware Statistical Analysis Framework for Aging Sensors Insertion. - Julio César Vázquez; Víctor H. Champac; Jorge Semião; Isabel C. Teixeira; Marcelino B. Santos; João Paulo Teixeira 001 (J. Electron. Test., 2013)

Possibilities of defect-size magnification for testing resistive-opens in nanometer technologies. - Jose Luis Garcia-Gervacio; Jaime Martínez-Castillo; Víctor H. Champac (LATW, 2014)

Analysis of fin height on FinFET SRAM cell hardening. - Hector Villacorta; Jaume Segura 001; Sebastià A. Bota; Víctor H. Champac (MWSCAS, 2014)

Hot topic session 12B: Stay relevant with standards-based DFT. - C. J. Clark; Víctor H. Champac (VTS, 2014)

Skew violation verification in digital interconnect signals based on signal addition. - Víctor H. Champac; Hector Villacorta; Nestor Hernandez; Joan Figueras (IEICE Electron. Express, 2014)

Message from the LATS2015 Chairs. - Víctor H. Champac; Yervant Zorian; Letícia Maria Bolzani Pöhls; Vishwani D. Agrawal (LATS, 2015)

Effective selection of favorable gates in BTI-critical paths to enhance circuit reliability. - Andres F. Gomez; Víctor H. Champac (LATS, 2015)

Impact of increasing the fin height on soft error rate and static noise margin in a FinFET-based SRAM cell. - Hector Villacorta; Roberto Gómez 001; Sebastià A. Bota; Jaume Segura 001; Víctor H. Champac (LATS, 2015)

Circuit performance optimization for local intra-die process variations using a gate selection metric. - Víctor H. Champac; Alejandra Nicte-ha Reyes; Andres F. Gomez (VLSI-SoC, 2015)

A new sizing approach for lifetime improvement of nanoscale digital circuits due to BTI aging. - Andres F. Gomez; Víctor H. Champac (VLSI-SoC, 2015)

An early prediction methodology for aging sensor insertion to assure safe circuit operation due to NBTI aging. - Andres F. Gomez; Leticia B. Poehls; Fabian Vargas 001; Víctor H. Champac (VTS, 2015)

Low VDD and body bias conditions for testing bridge defects in the presence of process variations. - Hector Villacorta; Jose Luis Garcia-Gervacio; Jaume Segura 001; Víctor H. Champac (Microelectron. J., 2015)

Screening small-delay defects using inter-path correlation to reduce reliability risk. - Jose Luis Garcia-Gervacio; Alejandro Nocua; Víctor H. Champac (Microelectron. Reliab., 2015)

Behavior and test of open-gate defects in FinFET based cells. - Francisco Mesalles; Hector Villacorta; Michel Renovell; Víctor H. Champac (ETS, 2016)

Critical path selection under NBTI/PBTI aging for adaptive frequency tuning. - Andres F. Gomez; Víctor H. Champac (EWDTS, 2016)

A methodology for NBTI circuit reliability at reduced power consumption using dual supply voltage. - Freddy Forero; Andres F. Gomez; Víctor H. Champac (LATS, 2016)

Impact of Fin-Height on SRAM Soft Error Sensitivity and Cell Stability. - Hector Villacorta; Jaume Segura 001; Víctor H. Champac (J. Electron. Test., 2016)

Improvement of Negative Bias Temperature Instability Circuit Reliability and Power Consumption Using Dual Supply Voltage. - Freddy Forero; Andres F. Gomez; Víctor H. Champac (J. Low Power Electron., 2016)

Effectiveness of a hardware-based approach to detect resistive-open defects in SRAM cells under process variations. - Andres F. Gomez; Felipe Lavratti; Guilherme Medeiros Machado; M. Sartori; Letícia Maria Veiras Bolzani; Víctor H. Champac; Fabian Vargas 001 (Microelectron. Reliab., 2016)

Early Selection of Critical Paths for Reliable NBTI Aging-Delay Monitoring. - Andres F. Gomez; Víctor H. Champac (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process Variations. - Jesús Moreno; Michel Renovell; Víctor H. Champac (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Analysis of short defects in FinFET based logic cells. - Freddy Forero; Jean-Marc Gallière; Michel Renovell; Víctor H. Champac (LATS, 2017)

A metric-guided gate-sizing methodology for aging guardband reduction. - Andres F. Gomez; Roberto Gómez 001; Víctor H. Champac (LATS, 2018)

Analysis of Bridge Defects in STT-MRAM Cells Under Process Variations and a Robust DFT Technique for Their Detection. - Víctor H. Champac; Andres F. Gomez; Freddy Forero; Kaushik Roy 001 (VLSI-SoC (Selected Papers), 2018)

Robust Detection of Bridge Defects in STT-MRAM Cells Under Process Variations. - Andres F. Gomez; Freddy Forero; Kaushik Roy 001; Víctor H. Champac (VLSI-SoC, 2018)

An accurate novel gate-sizing metric to optimize circuit performance under local intra-die process variations. - Zahira Perez; Hector Villacorta; Víctor H. Champac (VLSI-SoC, 2018)

Detectability Challenges of Bridge Defects in FinFET Based Logic Cells. - Freddy Forero; Jean-Marc Gallière; Michel Renovell; Víctor H. Champac (J. Electron. Test., 2018)

Selection of Critical Paths for Reliable Frequency Scaling under BTI-Aging Considering Workload Uncertainty and Process Variations Effects. - Andres F. Gomez; Víctor H. Champac (ACM Trans. Design Autom. Electr. Syst., 2018)

B-open: A New Defect in Nanometer Technologies due to SADP Process. - Freddy Forero; Michel Renovell; Víctor H. Champac (ETS, 2019)

A Semi-analytical Model for Interconnect Open Defects in FinFET Logic Cells. - Freddy Forero; Jean-Marc Gallière; Michel Renovell; Víctor H. Champac (LATS, 2019)

An Efficient Metric-Guided Gate Sizing Methodology for Guardband Reduction Under Process Variations and Aging Effects. - Andres F. Gomez; Víctor H. Champac (J. Electron. Test., 2019)

Modeling and Detectability of Full Open Gate Defects in FinFET Technology. - Freddy Forero; Hector Villacorta; Michel Renovell; Víctor H. Champac (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Analysis and detection of hard-to-detect full open defects in FinFET based SRAM cells. - Zahira Perez; Javier Mesalles; Hector Villacorta; Fabian Vargas 001; Víctor H. Champac (LATS, 2020)

Identification of Logic Paths Influenced by Severe Coupling Capacitances. - Ivan D. Meza-Ibarra; Víctor H. Champac; Roberto Gómez-Fuentes; Jose R. Noriega-Luna; A. Vera-Marquina (J. Electron. Test., 2020)

Analysis and Detection of Open-gate Defects in Redundant Structures of a FinFET SRAM Cell. - Víctor H. Champac; Javier Mesalles; Hector Villacorta; Fabian Vargas 001 (J. Electron. Test., 2021)

A New Defect Model due to a Dust Particle Affecting the Fingers of FinFET Logic Gates. - Víctor H. Champac; Freddy Forero; Michel Renovell; Leonardo Miceli (LATS, 2023)

B-open Defect: A Novel Defect Model in FinFET Technology. - Freddy Forero; Víctor H. Champac; Michel Renovell (ACM J. Emerg. Technol. Comput. Syst., 2023)

Fault Analysis for a MTJ-based Spiking Neural Network. - Leonardo Miceli; Elena-Ioana Vatajelu; Víctor H. Champac (LATS, 2024)

Failure Probability due to Radiation-Induced Effects in FinFET SRAM Cells under Process Variations. - Víctor H. Champac; Hector Villacorta; Roberto Gómez-Fuentes; Fabian Vargas 001; Jaume Segura 001 (J. Electron. Test., 2024)

Investigating Manufacturing Defects Leading to Potential Silent Data Errors. - Jorge Lopez; Víctor H. Champac (LATS, 2025)

Cost-Effective Analytical Models of Resistive Opens Defects in FinFET Technology. - Gustavo Aguirre; Freddy Forero; Víctor H. Champac; Michel Renovell; Florence Azaïs; Mariane Comte; Jean-Marc Gallière (IEEE Trans. Very Large Scale Integr. Syst., 2025)