A Hybrid Mesh Generation Method for Two and Three Dimensional Simulation of Semiconductor Processes and Devices. - Dan Wake; Klas Lilja; Victor Moroz (IMR, 1998)

Stress-Aware Design Methodology. - Victor Moroz; Lee Smith; Xi-Wei Lin; Dipu Pramanik; Greg Rollins (ISQED, 2006)

Bringing Manufacturing into Design via Process-Dependent SPICE Models. - Sridhar Tirumala; Yuri Mahotin; Xiao Lin; Victor Moroz; Lee Smith; S. Krishnamurthy; L. Bomholt; Dipu Pramanik (ISQED, 2006)

Analysis of performance and reliability trade-off in dummy pattern design for 32-nm technology. - Aditya P. Karmarkar; Xiaopeng Xu; Victor Moroz; Greg Rollins; Xiao Lin (ISQED, 2009)

Layout Proximity Effects and Modeling Alternatives for IC Designs. - Xi-Wei Lin; Victor Moroz (IEEE Des. Test Comput., 2010)

A CMOS-compatible boosted transistor having >2× drive current and low leakage current. - Jin-Woo Han; Victor Moroz; Andrey Kucherov; Dinesh Maheshwari; Valentin Abramzon; Zvi Or-Bach; Yoshio Nishi; Yuniarto Widjaja (ESSDERC, 2016)

Technology Inflection Points. - Victor Moroz (ISPD, 2016)

Transistor design for 5nm and beyond: Slowing down electrons to speed up transistors. - Victor Moroz; Joanne Huang; Reza Arghavani (ISQED, 2016)

TCAD modeling for reliability. - Paul Pfäffli; Hiu Yung Wong; X. Xu; Luca Silvestri; X. W. Lin; T. Yang; Ravi Tiwari; Souvik Mahapatra; Steve Motzny; Victor Moroz; Terry Ma (Microelectron. Reliab., 2018)

Gate-All-Around Technology is Coming.: What's Next After GAA? - Victor Moroz (ISPD, 2023)

Exploring Power Savings of Gate-All-Around Cryogenic Technology. - Victor Moroz; Alexei Svizhenko; Munkang Choi; Plamen Asenov; Jaehyun Lee (VLSI Technology and Circuits, 2023)

3DIC System-Technology Co-Optimization with a Focus on the Interplay of Thermal, Power, Timing, and Stress Effects. - Victor Moroz; Xiaopeng Xu; Alexei Svizhenko; Xi-Wei Lin; Sergey Popov; Henry Sheng; Kenneth Larsen (VLSI Technology and Circuits, 2024)