An Academic RISC-V Silicon Implementation Based on Open-Source Components. - Jaume Abella 001; Calvin Bulla; Guillem Cabo; Francisco J. Cazorla; Adrián Cristal; Max Doblas; Roger Figueras; Alberto González 004; Carles Hernández 001; César Hernández; Víctor Jiménez; Leonidas Kosmidis; et al. (DCIS, 2020)

On the use of many-core Marvell ThunderX2 processor for HPC workloads. - Víctor Soria Pardos; Adrià Armejach; Darío Suárez Gracia; Miquel Moretó (J. Supercomput., 2021)

DVINO: A RISC-V Vector Processor Implemented in 65nm Technology. - Guillem Cabo; Gerard Candón; Xavier Carril; Max Doblas; Marc Domínguez; Alberto González 004; César Hernández; Víctor Jiménez; Vatistas Kostalampros; Rubén Langarita; Neiel Leyva; Guillem López-Paradís; et al. (DCIS, 2022)

Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI. - Víctor Soria Pardos; Max Doblas; Guillem López-Paradís; Gerard Candón; Narcís Rodas; Xavier Carril; Pau Fontova-Musté; Neiel Leyva; Santiago Marco-Sola; Miquel Moretó (DSD, 2022)

Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology. - Max Doblas; Gerard Candón; Xavier Carril; Marc Domínguez; Enric Erra; Alberto González 004; César Hernández; Víctor Jiménez; Vatistas Kostalampros; Rubén Langarita; Neiel Leyva; Guillem López-Paradís; et al. (DCIS, 2023)

DynAMO: Improving Parallelism Through Dynamic Placement of Atomic Memory Operations. - Víctor Soria Pardos; Adrià Armejach; Tiago Mück; Darío Suárez Gracia; José A. Joao; Alejandro Rico; Miquel Moretó (ISCA, 2023)

A Tensor Marshaling Unit for Sparse Tensor Algebra on General-Purpose Processors. - Marco Siracusa; Víctor Soria Pardos; Francesco Sgherzi; Joshua Randall 001; Douglas J. Joseph; Miquel Moretó Planas; Adrià Armejach (MICRO, 2023)

GenArchBench: A genomics benchmark suite for arm HPC processors. - Lorién López-Villellas; Rubén Langarita-Benítez; Asaf Badouh; Víctor Soria Pardos; Quim Aguado-Puig; Guillem López-Paradís; Max Doblas; Javier Setoain; Chulho Kim; Makoto Ono; Adrià Armejach; Santiago Marco-Sola; et al. (Future Gener. Comput. Syst., 2024)

Ember: A Compiler for Efficient Embedding Operations on Decoupled Access-Execute Architectures. - Marco Siracusa; Olivia Hsu; Víctor Soria Pardos; Joshua Randall 001; Arnaud Grasset; Eric Biscondi; Douglas J. Joseph; Randy Allen; Fredrik Kjolstad; Miquel Moretó Planas; Adrià Armejach (CoRR, 2025)