New Frontiers: Self-Assembly and Nanoelectronics. - Victor V. Zhirnov; Daniel J. C. Herr (Computer, 2001)

Limits to binary logic switch scaling - a gedanken model. - Victor V. Zhirnov; Ralph K. Cavin III; James A. Hutchby; George Bourianoff (Proc. IEEE, 2003)

Future devices for information processing. - Ralph K. Cavin III; Victor V. Zhirnov (ESSCIRC, 2005)

The Viability of Cellular Automata Architectures for General Purpose Computing. - Victor V. Zhirnov; Greg Leeming; Kosmas Galatsis; Ralph K. Cavin III (ERSA, 2008)

Boolean Logic and Alternative Information-Processing Devices. - George Bourianoff; Joe E. Brewer; Ralph K. Cavin III; James A. Hutchby; Victor V. Zhirnov (Computer, 2008)

Emerging Research Architectures. - Ralph K. Cavin III; James A. Hutchby; Victor V. Zhirnov; Joe E. Brewer; George Bourianoff (Computer, 2008)

Emerging Nanoscale Memory and Logic Devices: A Critical Assessment. - James A. Hutchby; Ralph K. Cavin III; Victor V. Zhirnov; Joe E. Brewer; George Bourianoff (Computer, 2008)

An Assessment of Integrated Digital Cellular Automata Architectures. - Victor V. Zhirnov; Ralph K. Cavin III; Greg Leeming; Kosmas Galatsis (Computer, 2008)

Scaling beyond CMOS: Turing-Heisenberg Rapproachment. - Victor V. Zhirnov; Ralph K. Cavin III (ESSCIRC, 2009)

Memory Devices: Energy-Space-Time Tradeoffs. - Victor V. Zhirnov; Ralph K. Cavin III; Stephan Menzel; Eike Linn; Sebastian Schmelzer; Dennis Bräuhaus; Christina Schindler; Rainer Waser (Proc. IEEE, 2010)

Prolog to the Section on Science and Engineering Beyond Moore's Law. - Ralph K. Cavin III; Paolo Lugli; Victor V. Zhirnov (Proc. IEEE, 2012)

Science and Engineering Beyond Moore's Law. - Ralph K. Cavin III; Paolo Lugli; Victor V. Zhirnov (Proc. IEEE, 2012)

Nurturing the Growth of a National Infrastructure in Emerging Technologies. - Rafic Z. Makki; Victor V. Zhirnov; Ralph K. Cavin III; Sami Issa; Marco Iansiti (Proc. IEEE, 2018)