The energy complexity of register files. - Victor V. Zyuban; Peter M. Kogge (ISLPED, 1998)

Application of STD to latch-power estimation. - Victor V. Zyuban; Peter M. Kogge (IEEE Trans. Very Large Scale Integr. Syst., 1999)

Optimization of high-performance superscalar architectures for energy efficiency. - Victor V. Zyuban; Peter M. Kogge (ISLPED, 2000)

Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors. - David M. Brooks; Pradip Bose; Stanley Schuster; Hans M. Jacobson; Prabhakar Kudva; Alper Buyuktosunoglu; John-David Wellman; Victor V. Zyuban; Manish Gupta; Peter W. Cook (IEEE Micro, 2000)

Clocking strategies and scannable latches for low power appliacations. - Victor V. Zyuban; David Meltzer (ISLPED, 2001)

Inherently Lower-Power High-Performance Superscalar Architectures. - Victor V. Zyuban; Peter M. Kogge (IEEE Trans. Computers, 2001)

Unified architecture level energy-efficiency metric. - Victor V. Zyuban (ACM Great Lakes Symposium on VLSI, 2002)

Low power integrated scan-retention mechanism. - Victor V. Zyuban; Stephen V. Kosonocky (ISLPED, 2002)

Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels. - Victor V. Zyuban; Philip N. Strenski (ISLPED, 2002)

Optimizing pipelines for power and performance. - Viji Srinivasan; David M. Brooks; Michael Gschwind; Pradip Bose; Victor V. Zyuban; Philip N. Strenski; Philip G. Emma (MICRO, 2002)

Early-Stage Definition of LPX: A Low Power Issue-Execute Processor. - Pradip Bose; David M. Brooks; Alper Buyuktosunoglu; Peter W. Cook; K. Das; Philip G. Emma; Michael Gschwind; Hans M. Jacobson; Tejas Karkhanis; Prabhakar Kudva; Stanley Schuster; James E. Smith 001; et al. (PACS, 2002)

Low-power circuits and technology for wireless digital systems. - Stephen V. Kosonocky; Azeez J. Bhavnagarwala; Kenneth Chin; George Gristede; Anne-Marie Haen; Wei Hwang; Mark B. Ketchen; Suhwan Kim 001; Daniel R. Knebel; Kevin W. Warren; Victor V. Zyuban (IBM J. Res. Dev., 2003)

An innovative low-power high-performance programmable signal processor for digital communications. - Jaime H. Moreno; Victor V. Zyuban; Uzi Shvadron; Fredy D. Neeser; Jeff H. Derby; Malcolm S. Ware; Krishnan Kailas; Ayal Zaks; Amir B. Geva; Shay Ben-David; Sameh W. Asaad; Thomas W. Fox; et al. (IBM J. Res. Dev., 2003)

Balancing hardware intensity in microprocessor pipelines. - Victor V. Zyuban; Philip N. Strenski (IBM J. Res. Dev., 2003)

Optimization of scannable latches for low energy. - Victor V. Zyuban (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Design methodology for semi custom processor cores. - Victor V. Zyuban; Sameh W. Asaad; Thomas W. Fox; Anne-Marie Haen; Daniel Littrell; Jaime H. Moreno (ACM Great Lakes Symposium on VLSI, 2004)

Microarchitectural techniques for power gating of execution units. - Zhigang Hu; Alper Buyuktosunoglu; Viji Srinivasan; Victor V. Zyuban; Hans M. Jacobson; Pradip Bose (ISLPED, 2004)

Integrated Analysis of Power and Performance for Pipelined Microprocessors. - Victor V. Zyuban; David M. Brooks; Viji Srinivasan; Michael Gschwind; Pradip Bose; Philip N. Strenski; Philip G. Emma (IEEE Trans. Computers, 2004)

Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors. - Hans M. Jacobson; Pradip Bose; Zhigang Hu; Alper Buyuktosunoglu; Victor V. Zyuban; Richard J. Eickemeyer; Lee Eisen; John Griswell; Doug Logan; Balaram Sinharoy; Joel M. Tendler (HPCA, 2005)

Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling. - Rakesh Kumar 002; Victor V. Zyuban; Dean M. Tullsen (ISCA, 2005)

A Framework for Architecture-Level Lifetime Reliability Modeling. - Jeonghee Shin; Victor V. Zyuban; Zhigang Hu; Jude A. Rivers; Pradip Bose (DSN, 2007)

A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime. - Jeonghee Shin; Victor V. Zyuban; Pradip Bose; Timothy Mark Pinkston (ISCA, 2008)

The opportunity cost of low power design: a case study in circuit tuning. - Matthew M. Ziegler; Victor V. Zyuban; George Gristede; Milena Vratonjic; Joshua Friedrich (ISLPED, 2009)

A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR). - Milena Vratonjic; Matthew M. Ziegler; George Gristede; Victor V. Zyuban; Thomas Mitchell; Ee Cho; Chandu Visweswariah; Vojin G. Oklobdzija (PATMOS, 2009)

Power-efficient, reliable microprocessor architectures: modeling and design methods. - Pradip Bose; Alper Buyuktosunoglu; Chen-Yong Cher; John A. Darringer; Meeta Sharma Gupta; Hendrik F. Hamann; Hans M. Jacobson; Prabhakar Kudva; Eren Kursun; Niti Madan; Indira Nair; Jude A. Rivers; et al. (ACM Great Lakes Symposium on VLSI, 2010)

POWER7TM local clocking and clocked storage elements. - James D. Warnock; Leon J. Sigal; Dieter F. Wendel; K. Paul Muller; Joshua Friedrich; Victor V. Zyuban; Ethan H. Cannon; A. J. KleinOsowski (ISSCC, 2010)

The implementation of POWER7TM: A highly parallel and scalable multi-core high-end server processor. - Dieter F. Wendel; Ronald N. Kalla; Robert Cargnoni; Joachim G. Clabes; Joshua Friedrich; Roland Frech; James A. Kahle; Balaram Sinharoy; William J. Starke; Scott A. Taylor; Steve Weitzel; Sam G. Chu; et al. (ISSCC, 2010)

POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor. - Dieter F. Wendel; Ronald N. Kalla; James D. Warnock; Robert Cargnoni; Sam G. Chu; Joachim G. Clabes; Daniel Dreps; David Hrusecky; Joshua Friedrich; Md. Saiful Islam 004; James A. Kahle; Jens Leenstra; et al. (IEEE J. Solid State Circuits, 2011)

Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis. - Nagu R. Dhanwada; David J. Hathaway; Victor V. Zyuban; Peng Peng; Karl Moody; William W. Dungan; Arun Joseph; Rahul M. Rao; Christopher J. Gonzalez (ICCAD, 2013)

Power reduction by aggressive synthesis design space exploration. - Matthew M. Ziegler; George Gristede; Victor V. Zyuban (ISLPED, 2013)

Runtime power reduction capability of the IBM POWER7+ chip. - Michael S. Floyd; Alan J. Drake; Nicole S. Schwartz; Robert W. Berry; Charles Lefurgy; Malcolm S. Ware; Karthick Rajamani; Victor V. Zyuban; Richard L. Willaman; Ruby M. Zgabay (IBM J. Res. Dev., 2013)

IBM POWER7+ design for higher frequency at fixed power. - Victor V. Zyuban; Scott A. Taylor; Birger Christensen; A. R. Hall; Christopher J. Gonzalez; Joshua Friedrich; Frances Clougherty; Jon Tetzloff; Rajeev R. Rao (IBM J. Res. Dev., 2013)

POWER8 design methodology innovations for improving productivity and reducing power. - Matthew M. Ziegler; Ruchir Puri; Bob Philhower; Robert L. Franch; Wing K. Luk; Jens Leenstra; Peter Verwegen; Niels Fricke; George Gristede; Eric Fluhr; Victor V. Zyuban (CICC, 2014)

The POWER8TM processor: Designed for big data, analytics, and cloud environments. - Joshua Friedrich; Hung Q. Le; William J. Starke; Jeff Stuecheli; Balaram Sinharoy; Eric J. Fluhr; Daniel M. Dreps; Victor V. Zyuban; Gregory S. Still; Christopher J. Gonzalez; David Hogenmiller; Frank Malgioglio; et al. (ICICDT, 2014)

5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth. - Eric J. Fluhr; Joshua Friedrich; Daniel M. Dreps; Victor V. Zyuban; Gregory S. Still; Christopher J. Gonzalez; Allen Hall; David Hogenmiller; Frank Malgioglio; Ryan Nett; Jose Paredes; Juergen Pille; et al. (ISSCC, 2014)

Session 8 overview: Low-power digital techniques: Energy-efficient digital. - Victor V. Zyuban; Peter Nilsson 001 (ISSCC, 2015)

IBM POWER8 circuit design and energy optimization. - Victor V. Zyuban; Joshua Friedrich; Daniel M. Dreps; Jürgen Pille; Donald W. Plass; Phillip J. Restle; Zeynep Toprak Deniz; Matthew M. Ziegler; Sam G. Chu; Md. Saiful Islam 004; James D. Warnock; Bob Philhower; et al. (IBM J. Res. Dev., 2015)

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. - Eric J. Fluhr; Steve Baumgartner; David W. Boerstler; John F. Bulzacchelli; Timothy Diemoz; Daniel Dreps; George English; Joshua Friedrich; Anne Gattiker; Tilman Gloekler; Christopher J. Gonzalez; Jason Hibbeler; et al. (IEEE J. Solid State Circuits, 2015)